Datasheet

USBLC6-2 Technical information
Doc ID 11265 Rev 5 9/14
2.6 PSpice model
Figure 16. shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are
defined by the PSpice parameters given in Figure 17.
Figure 16. PSpice model
Note: This simulation model is available only for an ambient temperature of 27 °C.
MODEL = Dlow MODEL = Dhigh
VBUS
LI/O
LGND
GND
D+in
MODEL = Dzener
RI/O
LI/O
D-in
RI/O
LI/O
LI/O
RGND RI/O
D-out
RI/O
MODEL = Dlow MODEL = Dhigh
LI/O
D+out
RI/O
Figure 17. PSpice parameters Figure 18. USBLC6-2 PCB layout
considerations
Dlow Dhigh Dzener
BV 50 50 7.3
CJ0 0.9p 2.0p 40p
IBV 1m 1m 1m
M 0.3333 0.3333 0.3333
RS 0.2 0.52 0.84
VJ 0.6 0.6 0.6
TT 0.1u 0.1u 0.1u
LI/O 750p
RI/O 110m
LGND 550p
RGND 60m
D+in
D+out
D-out
GND
USBLC6-2
D-in
V
BUS
1
C = 100nF
BUS