Datasheet

Electrical characteristics
TSV632, TSV632A, TSV633, TSV633A, TSV634,
TSV634A, TSV635, TSV635A
8/31
DocID15688 Rev 6
Table 6: VCC+ = 3.3 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, RL connected to VCC/2
(unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
V
io
Offset voltage
TSV63x
3
mV
TSV63xA
0.8
TSV633AIST (MiniSO10)
1
T
min
< T
op
< T
max
- TSV63x
4.5
T
min
< T
op
< T
max
- TSV63xA
2
T
min
< T
op
< T
max
- TSV633AIST
2.2
∆V
io
/∆T
Input offset voltage drift
2
μV/°C
I
io
Input offset current
V
out
= V
CC
/2
1
10
(1)
pA
T
min
< T
op
< T
max
1
100
I
ib
Input bias current
V
out
= V
CC
/2
1
10
(1)
T
min
< T
op
< T
max
1
100
CMR
Common mode rejection
ratio 20 log (ΔV
ic
/ΔV
io
)
0 V to 3.3 V, V
out
= 1.65 V
57
79
dB
T
min
< T
op
< T
max
53
A
vd
Large signal voltage gain
R
L
= 10 kΩ, V
out
= 0.5 V to 2.8 V
88
98
T
min
< T
op
< T
max
83
V
OH
High level output voltage,
(V
OH
= V
CC
- V
out
)
R
L
= 10 kΩ
5
35
mV
T
min
< T
op
< T
max
50
V
OL
Low level output voltage
R
L
= 10 kΩ
4
35
T
min
< T
op
< T
max
50
I
out
I
sink
V
o
= 3.3 V
23
45
mA
T
min
< T
op
< T
max
20
I
source
V
o
= 0 V
23
38
T
min
< T
op
< T
max
20
I
CC
Supply current,
(per channel)
No load, V
out
= 1.75 V
43
55
64
µA
T
min
< T
op
< T
max
66
AC performance
GBP
Gain bandwidth product
R
L
= 2 kΩ, C
L
= 100 pF,
f = 100 kHz
710
860
kHz
ɸm
Phase margin
R
L
= 2 kΩ, C
L
= 100 pF
46
Degrees
G
m
Gain margin
R
L
= 2 kΩ, C
L
= 100 pF
13
dB
SR
Slew rate
R
L
= 2 kΩ, C
L
= 100 pF, A
V
= 1
0.22
0.29
V/μs
Notes:
(1)
Guaranteed by design