Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Package pin connections
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- Table 4. Electrical characteristics at VCC+ = +2.7 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Table 5. Electrical characteristics at VCC+ = +3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Table 6. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Figure 2. Supply current vs. supply voltage at Vicm = VCC/2
- Figure 3. Input offset voltage distribution at VCC = 5 V, Vicm = 2.5 V
- Figure 4. Input offset voltage temperature coefficient distribution
- Figure 5. Input offset voltage vs. input common mode voltage at VCC = 5 V
- Figure 6. Input offset voltage vs. temperature at VCC = 5 V
- Figure 7. Output current vs. output voltage at VCC = 2.7 V
- Figure 8. Output current vs. output voltage at VCC = 5.5 V
- Figure 9. Bode diagram at VCC = 2.7 V, RL = 10 kW
- Figure 10. Bode diagram at VCC = 2.7 V, RL = 2 kW
- Figure 11. Bode diagram at VCC = 5.5 V, RL = 10 kW
- Figure 12. Bode diagram at VCC = 5.5 V, RL = 2 kW
- Figure 13. Noise vs. frequency
- Figure 14. Positive slew rate vs. supply voltage
- Figure 15. Negative slew rate vs. supply voltage
- Figure 16. THD+N vs. frequency at VCC = 2.7 V
- Figure 17. THD+N vs. frequency at VCC = 5.5 V
- Figure 18. THD+N vs. output voltage at VCC = 2.7 V
- Figure 19. THD+N vs. output voltage at VCC = 5.5 V
- Figure 20. Output impedance versus frequency in closed-loop configuration
- Figure 21. Response to a 100 mV input step for gain = 1 at VCC = 5.5 V rising edge
- Figure 22. Response to a 100 mV input step for gain = 1 at VCC = 5.5 V falling edge
- Figure 23. PSRR vs. frequency at VCC = 2.7 V
- Figure 24. PSRR vs. frequency at VCC = 5.5 V
- 4 Application information
- 5 Package information
- Figure 30. SC70-5 package outline
- Table 7. SC70-5 package mechanical data
- Figure 31. DFN8 2 x 2 x 0.6, 8 pitch, 0.5 mm package outline
- Table 8. DFN8 2 x 2 x 0.6, 8 pitch, 0.5 mm package mechanical data
- Figure 32. DFN8 2 x 2 0.6, 8 pitch, 0.5 mm footprint recommendation
- Figure 33. MiniSO8 package outline
- Table 9. MiniSO8 package mechanical data
- Figure 34. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - package outline
- Table 10. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - package mechanical data
- Figure 35. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - footprint recommendation
- Figure 36. TSSOP14 body 4.40 mm, lead pitch 0.65 mm - package outline
- Table 11. TSSOP14 body 4.40 mm, lead pitch 0.65 mm - package mechanical data
- 6 Ordering information
- 7 Revision history

Electrical characteristics TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
6/27 Doc ID 022743 Rev 1
e
n
Equivalent input noise
voltage
f = 1 kHz
f = 10 kHz
61
43
THD+N
Total harmonic distortion +
noise
Follower configuration, f
in
= 1 kHz,
R
L
= 100 kΩ, V
icm
= V
CC
/2,
BW = 22 kHz, V
out
= 1 V
pp
0.003 %
Table 4. Electrical characteristics at V
CC+
= +2.7 V with V
CC-
= 0 V, V
icm
= V
CC
/2, T = 25 °C, and
R
L
=10kΩ connected to V
CC
/2 (unless otherwise specified) (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
nV
Hz
------------
Table 5. Electrical characteristics at V
CC+
= +3.3 V with V
CC-
= 0 V, V
icm
= V
CC
/2, T = 25 °C, and
R
L
=10kΩ connected to V
CC
/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
V
io
Offset voltage
TSV52xA, T = 25 °C 600 µV
TSV52xA, -40 °C < T < 125 °C 2400 µV
TSV52x, T = 25 °C 1.3 mV
TSV52x, -40 °C < T < 125 °C 3.1 mV
ΔV
io
/ΔT Input offset voltage drift -40 °C < T < 125 °C
(1)
318µV/°C
ΔV
io
Long term input offset
voltage drift
T = 25 °C
(2)
0.3
I
io
Input offset current
(V
out
=V
CC
/2)
T = 25 °C 1 10
(3)
pA
-40 °C < T < 125 °C 1 100
(3)
pA
I
ib
Input bias current
(V
out
=V
CC
/2)
T = 25 °C 1 10
(3)
pA
-40 °C < T < 125 °C 1 100
(3)
pA
CMR
Common mode rejection
ratio 20 log (ΔV
ic
/ΔV
io
)
V
ic
= -0.1 V to V
CC
+0.1 V,
V
out
= V
CC
/2, R
L
=1MΩ
T = 25 °C 51 73
dB
-40 °C < T < 125 °C 47
A
vd
Large signal voltage gain
V
out
= 0.5 V to (V
CC
- 0.5 V),
R
L
=1MΩ
T = 25 °C 91 106
dB
-40 °C < T < 125 °C 63
V
OH
High level output voltage
T = 25 °C
-40 °C < T < 125 °C
335
50
mV
V
OL
Low level output voltage
T = 25 °C
-40 °C < T < 125 °C
735
50
mV
I
out
I
sink
V
out
= V
CC
, T = 25 °C 20 31
mA
V
out
= V
CC
, -40 °C < T < 125 °C 17
I
source
V
out
= 0 V, T = 25 °C 19 27
mA
V
out
= 0 V, -40 °C < T < 125 °C 17
I
CC
Supply current (per channel)
V
out
=V
CC
/2, R
L
>1MΩ
T = 25 °C 32 55
µA
-40 °C < T < 125 °C 32 55
μV
month
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