Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Package pin connections
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- Table 4. Electrical characteristics at VCC+ = +2.7 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Table 5. Electrical characteristics at VCC+ = +3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Table 6. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Figure 2. Supply current vs. supply voltage at Vicm = VCC/2
- Figure 3. Input offset voltage distribution at VCC = 5 V, Vicm = 2.5 V
- Figure 4. Input offset voltage temperature coefficient distribution
- Figure 5. Input offset voltage vs. input common mode voltage at VCC = 5 V
- Figure 6. Input offset voltage vs. temperature at VCC = 5 V
- Figure 7. Output current vs. output voltage at VCC = 2.7 V
- Figure 8. Output current vs. output voltage at VCC = 5.5 V
- Figure 9. Bode diagram at VCC = 2.7 V, RL = 10 kW
- Figure 10. Bode diagram at VCC = 2.7 V, RL = 2 kW
- Figure 11. Bode diagram at VCC = 5.5 V, RL = 10 kW
- Figure 12. Bode diagram at VCC = 5.5 V, RL = 2 kW
- Figure 13. Noise vs. frequency
- Figure 14. Positive slew rate vs. supply voltage
- Figure 15. Negative slew rate vs. supply voltage
- Figure 16. THD+N vs. frequency at VCC = 2.7 V
- Figure 17. THD+N vs. frequency at VCC = 5.5 V
- Figure 18. THD+N vs. output voltage at VCC = 2.7 V
- Figure 19. THD+N vs. output voltage at VCC = 5.5 V
- Figure 20. Output impedance versus frequency in closed-loop configuration
- Figure 21. Response to a 100 mV input step for gain = 1 at VCC = 5.5 V rising edge
- Figure 22. Response to a 100 mV input step for gain = 1 at VCC = 5.5 V falling edge
- Figure 23. PSRR vs. frequency at VCC = 2.7 V
- Figure 24. PSRR vs. frequency at VCC = 5.5 V
- 4 Application information
- 5 Package information
- Figure 30. SC70-5 package outline
- Table 7. SC70-5 package mechanical data
- Figure 31. DFN8 2 x 2 x 0.6, 8 pitch, 0.5 mm package outline
- Table 8. DFN8 2 x 2 x 0.6, 8 pitch, 0.5 mm package mechanical data
- Figure 32. DFN8 2 x 2 0.6, 8 pitch, 0.5 mm footprint recommendation
- Figure 33. MiniSO8 package outline
- Table 9. MiniSO8 package mechanical data
- Figure 34. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - package outline
- Table 10. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - package mechanical data
- Figure 35. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - footprint recommendation
- Figure 36. TSSOP14 body 4.40 mm, lead pitch 0.65 mm - package outline
- Table 11. TSSOP14 body 4.40 mm, lead pitch 0.65 mm - package mechanical data
- 6 Ordering information
- 7 Revision history
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A Application information
Doc ID 022743 Rev 1 15/27
Figure 29. In series resistor versus capacitive load
4.6 Input offset voltage drift over temperature
The maximum input voltage drift over temperature variation is defined as the offset variation
related to offset value measured at 25 °C. The operational amplifier is one of the main
circuits of the signal conditioning chain, and the amplifier input offset is a major contributor
to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during
production at application level. The maximum input voltage drift over temperature enables
the system designer to anticipate the effects of temperature variations.
The maximum input voltage drift over temperature is computed in Equation 1:
Equation 1
with T = -40 °C and 125 °C.
The datasheet maximum value is guaranteed by measurement on a representative sample
size ensuring a Cpk greater than 2.
3TABLE
-INIMUMSERIALRESISTORTOBEADDEDTOAGIVEN
CAPACITIVELOADINORDERTOENSURESTABILITY
6
##
66
ICM
64#2
LOAD
5NSTABLE
#APACITIVELOADN&
!-
ΔV
io
ΔT
------ ---- -- max
V
io
T() V
io
25° C()–
T25° C–
---- --- --- ---- --- --- --- ----------------------------
=