Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Package pin connections
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- Table 4. Electrical characteristics at VCC+ = +2.7 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Table 5. Electrical characteristics at VCC+ = +3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Table 6. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Figure 2. Supply current vs. supply voltage at Vicm = VCC/2
- Figure 3. Input offset voltage distribution at VCC = 5 V, Vicm = 2.5 V
- Figure 4. Input offset voltage temperature coefficient distribution
- Figure 5. Input offset voltage vs. input common mode voltage at VCC = 5 V
- Figure 6. Input offset voltage vs. temperature at VCC = 5 V
- Figure 7. Output current vs. output voltage at VCC = 2.7 V
- Figure 8. Output current vs. output voltage at VCC = 5.5 V
- Figure 9. Bode diagram at VCC = 2.7 V, RL = 10 kW
- Figure 10. Bode diagram at VCC = 2.7 V, RL = 2 kW
- Figure 11. Bode diagram at VCC = 5.5 V, RL = 10 kW
- Figure 12. Bode diagram at VCC = 5.5 V, RL = 2 kW
- Figure 13. Noise vs. frequency
- Figure 14. Positive slew rate vs. supply voltage
- Figure 15. Negative slew rate vs. supply voltage
- Figure 16. THD+N vs. frequency at VCC = 2.7 V
- Figure 17. THD+N vs. frequency at VCC = 5.5 V
- Figure 18. THD+N vs. output voltage at VCC = 2.7 V
- Figure 19. THD+N vs. output voltage at VCC = 5.5 V
- Figure 20. Output impedance versus frequency in closed-loop configuration
- Figure 21. Response to a 100 mV input step for gain = 1 at VCC = 5.5 V rising edge
- Figure 22. Response to a 100 mV input step for gain = 1 at VCC = 5.5 V falling edge
- Figure 23. PSRR vs. frequency at VCC = 2.7 V
- Figure 24. PSRR vs. frequency at VCC = 5.5 V
- 4 Application information
- 5 Package information
- Figure 30. SC70-5 package outline
- Table 7. SC70-5 package mechanical data
- Figure 31. DFN8 2 x 2 x 0.6, 8 pitch, 0.5 mm package outline
- Table 8. DFN8 2 x 2 x 0.6, 8 pitch, 0.5 mm package mechanical data
- Figure 32. DFN8 2 x 2 0.6, 8 pitch, 0.5 mm footprint recommendation
- Figure 33. MiniSO8 package outline
- Table 9. MiniSO8 package mechanical data
- Figure 34. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - package outline
- Table 10. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - package mechanical data
- Figure 35. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - footprint recommendation
- Figure 36. TSSOP14 body 4.40 mm, lead pitch 0.65 mm - package outline
- Table 11. TSSOP14 body 4.40 mm, lead pitch 0.65 mm - package mechanical data
- 6 Ordering information
- 7 Revision history
Application information TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A
14/27 Doc ID 022743 Rev 1
4.3 Rail-to-rail input
The TSV52x series are guaranteed without phase reversal as shown in Figure 28.
It is extremely important that the current flowing in the input pin does not exceed 10 mA.
In order to limit this current a serial resistor can be added on the V
in
path.
4.4 Rail-to-rail output
The operational amplifiers output levels can go close to the rails: 35 mV maximum above
and below the rail when connected to a 10 kΩ resistive load to V
CC
/2.
4.5 Driving resistive and capacitive loads
To drive high capacitive load, adding in series resistor at the output can improve the stability
of the device (see Figure 29 for recommended in series value). Once the in series resistor
has been selected, the stability of the circuit should be tested on bench and simulated with
simulation models. The R
load
is placed in parallel with capacitive load. The R
load
and the
in series resistor create a voltage divider introducing an error proportional to the ratio
R
s
/R
load
. By choosing R
s
as low as possible, this error is generally negligible.
Figure 27. Phase reversal test schematic Figure 28. No phase reversal
6
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6
##
6
OUT
6
INP
6
6
!-
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6
##
6
6
INN
6
6
OUT
6
6
INP
6
!-