Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Package pin connections
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- Table 4. Electrical characteristics at VCC+ = +2.7 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Table 5. Electrical characteristics at VCC+ = +3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Table 6. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 C, and RL = 10 kW connected to VCC/2 (unless otherwise specified)
- Figure 2. Supply current vs. supply voltage at Vicm = VCC/2
- Figure 3. Input offset voltage distribution at VCC = 5 V, Vicm = 2.5 V
- Figure 4. Input offset voltage temperature coefficient distribution
- Figure 5. Input offset voltage vs. input common mode voltage at VCC = 5 V
- Figure 6. Input offset voltage vs. temperature at VCC = 5 V
- Figure 7. Output current vs. output voltage at VCC = 2.7 V
- Figure 8. Output current vs. output voltage at VCC = 5.5 V
- Figure 9. Bode diagram at VCC = 2.7 V, RL = 10 kW
- Figure 10. Bode diagram at VCC = 2.7 V, RL = 2 kW
- Figure 11. Bode diagram at VCC = 5.5 V, RL = 10 kW
- Figure 12. Bode diagram at VCC = 5.5 V, RL = 2 kW
- Figure 13. Noise vs. frequency
- Figure 14. Positive slew rate vs. supply voltage
- Figure 15. Negative slew rate vs. supply voltage
- Figure 16. THD+N vs. frequency at VCC = 2.7 V
- Figure 17. THD+N vs. frequency at VCC = 5.5 V
- Figure 18. THD+N vs. output voltage at VCC = 2.7 V
- Figure 19. THD+N vs. output voltage at VCC = 5.5 V
- Figure 20. Output impedance versus frequency in closed-loop configuration
- Figure 21. Response to a 100 mV input step for gain = 1 at VCC = 5.5 V rising edge
- Figure 22. Response to a 100 mV input step for gain = 1 at VCC = 5.5 V falling edge
- Figure 23. PSRR vs. frequency at VCC = 2.7 V
- Figure 24. PSRR vs. frequency at VCC = 5.5 V
- 4 Application information
- 5 Package information
- Figure 30. SC70-5 package outline
- Table 7. SC70-5 package mechanical data
- Figure 31. DFN8 2 x 2 x 0.6, 8 pitch, 0.5 mm package outline
- Table 8. DFN8 2 x 2 x 0.6, 8 pitch, 0.5 mm package mechanical data
- Figure 32. DFN8 2 x 2 0.6, 8 pitch, 0.5 mm footprint recommendation
- Figure 33. MiniSO8 package outline
- Table 9. MiniSO8 package mechanical data
- Figure 34. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - package outline
- Table 10. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - package mechanical data
- Figure 35. QFN16 - 3 x 3 x 0.9 mm, pad 1.7 - footprint recommendation
- Figure 36. TSSOP14 body 4.40 mm, lead pitch 0.65 mm - package outline
- Table 11. TSSOP14 body 4.40 mm, lead pitch 0.65 mm - package mechanical data
- 6 Ordering information
- 7 Revision history
TSV521, TSV522, TSV524, TSV521A, TSV522A, TSV524A Application information
Doc ID 022743 Rev 1 13/27
4 Application information
4.1 Operating voltages
The amplifiers of the TSV52x series can operate from 2.7 to 5.5 V. Their parameters are
fully specified for 2.7, 3.3 and 5 V power supplies. However, the parameters are very stable
in the full V
CC
range and several characterization curves show the TSV52x device
characteristics at 2.7 V. Additionally, the main specifications are guaranteed in extended
temperature ranges from -40 to +125 °C.
4.2 Common mode voltage range
The TSV52x devices are built with two complementary PMOS and NMOS input differential
pairs. The devices have a rail-to-rail input and the input common mode range is extended
from V
CC-
- 0.1 V to V
CC+
+0.1V.
The N channel pair is active for input voltage close to the positive rail typically (V
CC+
-0.7V)
to 100 mv above the positive rail.
The P channel pair is active for input voltage close to the negative rail typically 100 mV
below the negative rail to V
CC-
+0.7V.
And between V
CC-
+ 0.7 V and V
CC+
- 0.7 V the both N and P pairs are active.
When the both pairs work together it allows to increase the speed of the TSV52x device.
This architecture improves a lot the merit factor of the whole device. In the transition region,
the performance of CMR, SVR, V
io
(Figure 25 and Figure 26) and THD is slightly degraded.
Figure 25. Input offset voltage vs. input
common mode at V
CC
= 2.7 V
Figure 26. Input offset voltage vs. input
common mode at V
CC
= 5.5 V
6
IO
M6
6
ICM
6
!-
6
IO
M6
6
ICM
6
!-