Datasheet
Table Of Contents
- 1 Absolute maximum ratings and operating conditions
- 2 Schematic diagram
- 3 Electrical characteristics
- Table 3. VCC+ = 3 V, VCC- = 0 V, RL, CL connected to VCC/2, Tamb = 25 C (unless otherwise specified)
- Table 4. VCC+ = 5 V, VCC- = 0 V, RL, CL connected to VCC/2, Tamb = 25 C (unless otherwise specified)
- Table 5. VCC+ = 10 V, VCC- = 0 V, RL, CL connected to VCC/2, Tamb = 25 C (unless otherwise specified)
- Figure 2. Supply current (each amplifier) vs. supply voltage
- Figure 3. High level output voltage vs. high level output current (VCC = +5 V, VCC = +3 V)
- Figure 4. Low level output voltage vs. low level output current (VCC = +3 V, VCC = +5 V)
- Figure 5. Input bias current vs. temperature
- Figure 6. High level output voltage vs. high level output current (VCC = +16 V, VCC = +10 V)
- Figure 7. Low level output voltage vs. low level output current (VCC = 16 V, VCC = 10 V)
- Figure 8. Gain and phase vs. frequency (RL = 10 kW)
- Figure 9. Gain bandwidth product vs. supply voltage (RL = 10 kW)
- Figure 10. Phase margin vs. supply voltage (RL = 10 kW)
- Figure 11. Gain and phase vs. frequency (RL = 600 W)
- Figure 12. Gain bandwidth product vs. supply voltage (RL = 600 W)
- Figure 13. Phase margin vs. supply voltage (RL = 600 W)
- Figure 14. Input voltage noise vs. frequency
- 4 Macromodel
- 5 Package information
- 6 Ordering information
- 7 Revision history

TS912, TS912A, TS912B Electrical characteristics
Doc ID 2325 Rev 7 5/21
3 Electrical characteristics
Table 3. V
CC+
= 3 V, V
CC-
= 0 V, R
L
, C
L
connected to V
CC
/2, T
amb
= 25 °C
(unless otherwise specified)
Symbol Parameter Min. Typ. Max. Unit
V
io
Input offset voltage (V
ic
= V
o
= V
CC
/2)
TS912
TS912A
TS912B
T
min
≤ T
amb
≤ T
max
TS912
TS912A
TS912B
10
5
2
12
7
3
mV
ΔV
io
Input offset voltage drift 5 μV/°C
I
io
Input offset current
(1)
T
min
≤ T
amb
≤ T
max
1 100
200
pA
I
ib
Input bias current
(1)
T
min
≤ T
amb
≤ T
max
1 150
300
pA
I
CC
Supply current (per amplifier, A
VCL
= 1, no load)
T
min
≤ T
amb
≤ T
max
200 300
400
μA
CMR
Common mode rejection ratio
V
ic
= 0 to 3 V, V
o
= 1.5 V
70 dB
SVR Supply voltage rejection ratio (V
CC
+
= 2.7 to 3.3 V, V
o
= V
CC
/2) 50 80 dB
A
vd
Large signal voltage gain (R
L
= 10 kΩ, V
o
= 1.2 V to 1.8 V)
T
min
≤ T
amb
≤ T
max
3
2
10
V/mV
V
OH
High level output voltage (V
id
= 1 V)
R
L
= 100 kΩ
R
L
= 10 kΩ
R
L
= 600 Ω
R
L
= 100 Ω
T
min
≤ T
amb
≤ T
max
R
L
= 10 kΩ
R
L
= 600 Ω
2.95
2.9
2.3
2.8
2.1
2.96
2.6
2
V
V
OL
Low level output voltage (V
id
= -1 V)
R
L
= 100 kΩ
R
L
= 10 kΩ
R
L
= 600 Ω
R
L
= 100 Ω
T
min
≤ T
amb
≤ T
max
R
L
= 10 kΩ
R
L
= 600 Ω
30
300
900
50
70
400
100
600
mV
I
o
Output short-circuit current (V
id
= ±1 V)
Source (V
o
= V
CC-
)
Sink (V
o
= V
CC+
)
20
20
40
40
mA
GBP
Gain bandwidth product
(A
VCL
= 100, R
L
= 10 kΩ, C
L
= 100 pF, f = 100 kHz)
0.8 MHz