Datasheet
Table Of Contents
- 1 Absolute maximum ratings and operating conditions
- 2 Electrical characteristics
- Table 3. Electrical characteristics at VCC = +5 V, VDD = 0 V, Vicm = VCC/2, Tamb = 25 °C, RL connected to VCC/2 (unless otherwise specified)
- Table 4. Electrical characteristics at VCC = +3.3 V, VDD = 0 V, Vicm = VCC/2, Tamb = 25 °C, RL connected to VCC/2 (unless otherwise specified)
- Table 5. Electrical characteristics at VCC = +2.7 V VDD = 0 V, Vicm = VCC/2, Tamb = 25 °C, RL connected to VCC/2 (unless otherwise specified)
- Figure 1. Input offset voltage distribution for Vicm£ VCC-1.2 V at T=25 °C
- Figure 2. Input offset voltage distribution vs. temperature for Vicm£ VCC-1.2 V
- Figure 3. Input offset voltage distribution vs. temperature for Vicm ³ VCC-0.8 V
- Figure 4. Input offset voltage distribution for Vicm £ VCC-1.2 V at T=25 °C after HTB
- Figure 5. Input offset voltage distribution for Vicm £ VCC-1.2 V at T=25 °C after THB
- Figure 6. Input offset voltage vs. input common mode voltage at T=25 °C
- Figure 7. Supply current vs. input common mode voltage in closed loop configuration at VCC=5 V
- Figure 8. Supply current vs. supply voltage at Vicm=VCC/2
- Figure 9. Supply current vs. input common mode voltage in follower configuration at VCC=2.7 V
- Figure 10. Supply current vs. input common mode voltage in follower configuration at VCC=5 V
- Figure 11. Output current vs. supply voltage at Vicm=VCC/2
- Figure 12. Output current vs. output voltage at VCC=2.7 V
- Figure 13. Output current vs. output voltage at VCC=5 V
- Figure 14. Positive and negative slew rate vs. supply voltage
- Figure 15. Voltage gain and phase vs. frequency at VCC=5 V and Vicm=2.5 V at T=25 °C
- Figure 16. Voltage gain and phase vs. frequency at VCC=5 V and Vicm=2.5 V at T=-40 °C
- Figure 17. Voltage gain and phase vs. frequency at VCC=5 V and Vicm=2.5 V at T=125 °C
- Figure 18. Closed loop gain in voltage follower configuration for different capacitive load at T=25 °C
- Figure 19. Gain margin according to the output load, at VCC=5 V and T=25 °C
- Figure 20. Phase margin according to the output load, at VCC=5 V and T=25 °C
- Figure 21. Gain margin vs. output current, at VCC=5 V and T=25 °C
- Figure 22. Phase margin vs. output current, at VCC=5 V and T=25 °C
- Figure 23. Phase and gain margins vs capacitive load at = 25 °C
- Figure 24. Distortion + noise vs. output voltage
- Figure 25. Distortion + noise vs. frequency
- Figure 26. Noise vs. frequency
- 3 Application note
- 4 Package information
- 5 Ordering information
- 6 Revision history
Application note TS507
16/20 DocID10958 Rev 6
3.2 In-the-loop-compensation technique
The second technique is called in-the-loop-compensation technique, because the
additional components (a resistor and a capacitor) used to improve the stability are inserted
in the feedback loop (see Figure 30).
Figure 30. In-the-loop compensation schematics
This compensation method allows (by a good choice of compensation components) the
original pole caused by the capacitive load to be compensated. Stability is thus improved.
The main drawback of this circuit is the reduction of the output swing, because the isolation
resistor is in the signal path.
Table 6 shows the best compensation components for different ranges of load capacitors
(with R
L
= 10 kΩ) in voltage follower configuration.
Table 6. Best compensation components for different load capacitor ranges in
voltage follower configuration for TS507 (with R
L
= 10 kΩ)
Load capacitor
range
R
IL
(kΩ)C
IL
(pF)
Minimum gain
margin (dB)
(1)
1. Parameter guaranteed by design at 25 °C.
Minimum phase
margin (degree)
(1)
10 pF to 100 pF 1 250 17 55
100 pF to 1 nF 1 250 16 42
1 nF to 10 nF 1 630 11 27