Datasheet

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TDA7468

April 2010

1 FEATURES

 INPUT MULTIPLEXER

– 4 STEREO INPUTS

– SELECTABLE INPUT GAIN FOR OPTIMAL

ADAPTATION TO DIFFERENT SOURCES

 ONE STEREO OUTPUT

 BASS ALC

 TREBLE AND BASS CONTROL IN 2.0dB

 STEPS

 VOLUME CONTROL IN 1.0dB STEPS

 TWO SPEAKER ATTENUATORS:

– TWO INDEPENDENT SPEAKER CONTROL

IN 1.0dB STEPS FOR BALANCE FACILITY

– INDEPENDENT MUTE FUNCTION

 ALL FUNCTION ARE PROGRAMMABLE VIA

 SERIAL BUS

 EXTERNALLY ADJUSTABLE SURROUND

2 DESCRIPTION

The TDA7468D is a volume tone (bass and treble)

balance (Left/Right) processor for quality audio

applications in Hi-Fi systems.

Selectable input gain is provided. Control of all the

functions is accomplished by serial bus.

The AC signal setting is obtained by resistor net-

works and switches combined with operational

amplifiers.

Thanks to the used BIPOLAR/CMOS Technology,

Low Distortion, Low Noise and DC stepping are

obtained

TWO BANDS DIGITALLY CONTROLLED

AUDIO PROCESSOR WITH BASS ALC SURROUND

Figure 2. PIN CONNECTION (Top view)

IN4_L

MUX_L

IS_L

TREBLE_L

BASSI_L

OUT_L

BASSO_L

DGND

SCL

SDA

ALC

OUT_R

BASSI_R

BASSO_R

IS_R

MUX_R

TREBLE_R

IN4_R23

D99AU1057

MIC

IN1_L

IN2_L

IN3_L IN3_R

IN2_R

IN1_R

CREF

GND

Rev. 4

gure 1.

age

Table 1. Order Codes

Part Number Package

TDA7468D SO28

TDA7468D13TR Tape & Reel

SO28

Summary of content (23 pages)

PAGE 1
TDA7468 TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUND 1 2 FEATURES Figure 1. Package INPUT MULTIPLEXER – 4 STEREO INPUTS – SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT BASS ALC TREBLE AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: – TWO INDEPENDENT SPEAKER CONTROL IN 1.
PAGE 2
/23 IN-L4 IN-L3 IN-L2 IN-L1 ALC MIC-MIX IN-R1 IN-R2 IN-R3 IN-R4 50K 50K 50K 50K 50K 50K 50K 50K D99AU1058A 6 5 4 3 16 50K 2 26 25 24 23 INPUT SELECT 0dB, 6dB 10dB, 14dB INPUT SELECT + + MUX-L 7 buffer gain: 0 to 14dB gain / 2dB step buffer gain: 0 to 14dB gain / 2dB step 22 MUX-R IS-L 8 50K 50K 0dB 6dB 9dB 12dB VARIABLE MIX non-inverting inverting HALF_WAVE RECTIFIER BASS_ALC CONTROL 0dB VARIABLE MIX 6dB 9dB 12dB non-inverting inverting 21 IS-R + + +
PAGE 3
TDA7468 Table 2. ABSOLUTE MAXIMUM RATINGS Symbol VS Parameter Value Unit 10.5 V 0 to 70 °C -55 to 150 °C Value Unit 85 °C/W Operating Supply Voltage Tamb Operating Ambient Temperature Tstg Storage Temperature Range Table 3. THERMAL DATA Symbol Rth j-pin Parameter Thermal Resistance Junction-pins Table 4. QUICK REFERENCE DATA Symbol Parameter Min. Typ. Max. Unit 9 10 V VS Supply Voltage 5 VCL Max.
PAGE 4
TDA7468 ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, f = 1KHz all controls flat (G = 0dB), unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 5 9 10 V 9 mA 60 90 dB 35 50 2 2.
PAGE 5
TDA7468 ELECTRICAL CHARACTERISTICS (continua) (refer to the test circuit Tamb = 25°C, VS = 9V, f = 1KHz all controls flat (G = 0dB), unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit BASS CONTROL Gb BSTEP RB ±12.0 ±14.0 ±16.0 dB Step Resolution Control Range Max. Boost/cut 1 2 3 dB Internal Feedback Resistance 33 44 55 KΩ BASS ALC CONTROL Rattack1 Attack Time Resistor 1 12.
PAGE 6
/23 IN-R1 IN-R2 IN-R3 IN-R4 0.47µF 0.47µF 0.47µF 0.47µF 1M 0.47µF IN-L4 IN-L3 IN-L2 IN-L1 ALC 0.47µF MIC-MIX 0.47µF 0.47µF 0.47µF 0.
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TDA7468 3 APPLICATION SUGGESTIONS The first and the last stages are volume control blocks. The control range is 0 to -63dB (mute) with 1dB step resolution for this first one, 0 to 24dB (mute) with 8dB step resolution for the last one. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7468D audioprocessor provides 2 bands tones control. 3.1 Bass, Stages The Bass cell has an internal resistor Ri = 44KΩ typical.
PAGE 8
TDA7468 4 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7468D and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 4.1 Data Validity As shown in fig. 6, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 4.
PAGE 9
TDA7468 5 SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7468D address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P) SUBADDRESS CHIP ADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 DATA 1 to DATA n MSB ACK X LSB X X B DATA MSB ACK LSB DATA ACK P D96AU420 ACK = Acknowledge S = Start; P = Stop A = Address B = Auto Increment 6 EXAMPLES 6.
PAGE 10
TDA7468 7 DATA BYTES Address = (HEX) 10001000. Table 6.
PAGE 11
TDA7468 Table 8. INPUT GAIN SELECTION MSB D7 D6 D5 D4 D3 LSB INPUT GAIN D2 D1 D0 2dB STEPS 0 0 0 0dB 0 0 1 2dB 0 1 0 4dB 0 1 1 6dB 1 0 0 8dB 1 0 1 10dB 1 1 0 12dB 1 1 1 14dB GAIN = 0 to 30dB Table 9.
PAGE 12
TDA7468 Table 10. VOLUME MSB D7 D6 D5 D4 D3 LSB VOLUME D2 D1 D0 1dB STEPS 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 8dB STEPS 0 0 0 0dB 0 0 1 -8dB 0 1 0 -16dB 0 1 1 -24dB 1 0 0 -32dB 1 0 1 -40dB 1 1 0 -48dB 1 1 1 -56dB VOLUME 2 0 0 0dB 0 1 -8dB 1 0 -16dB 1 1 -24dB VOLUME = 0 to-87dB Table 11.
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TDA7468 Table 11.
PAGE 14
TDA7468 Table 11. VOLUME setting 1 (continua) -58 -2 -59 -3 -60 -4 -61 -5 -62 -6 -63 -7 -64 0 -65 -1 -66 -2 -67 -3 -68 -4 -69 -5 -70 -6 -71 -7 -72 0 -73 -1 -74 -2 -75 -3 -76 -4 -77 -5 -78 -6 -79 -7 -80 0 -81 -1 -82 -2 -83 -3 -84 -4 -85 -5 -86 -6 -87 -7 -56 8 -56 -16 -56 -24 Table 12.
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TDA7468 Table 12.
PAGE 16
TDA7468 Table 12.
PAGE 17
TDA7468 Table 13.
PAGE 18
TDA7468 Table 15. BASS ALC MSB D7 LSB D6 D5 D4 D3 D2 D1 BASS ALC D0 ALC Mode 1 ON 0 OFF Detector 1 ON 0 OFF Release Current Circuit 1 ON 0 OFF Attack Time Resistor 0 0 12.5KΩ 0 1 25KΩ 1 0 50KΩ 1 1 100KΩ Threshold 0 0 700mVrms 0 1 485mVrms 1 0 320mVrms 1 1 170mVrms Attack Mode 0 MODE 1: Fixed Resistor 1 MODE 2: Adaptive Figure 9. BASS ALC : Threshold curve VO (VRMS) 1 Figure 10. BASS ALC : THD D00AU1100 Supply Voltage : 9.
PAGE 19
TDA7468 8 IC1 Figure 11. PINS: IN1_L, IN1_R, IN2_L, IN2_R, IN3_L, IN3_R, IN4_L, IN4 _R, IS_L, IS_R, MIC Figure 15. PINS: BASSI_L, BASSI_R VS 20µA VS 20µA 45K GND 50K GND Vref BASSO-L,BASSO-R D99AU1096 D99AU1092 Figure 16. PINS: BASSO_L, BASSO_R Figure 12. PINS: OUT_L, OUT_R, IMUX_L, MUX_R VS 20µA VS 20µA 45K 10Ω GND BASSI-L,BASSI-R D99AU1097 GND D99AU1093 Figure 17. PIN: ALC Figure 13. PINS: TREBLE_L, TREBLE_R VS 20µA VS 20µA 100K GND 25K D99AU1098 GND D99AU1094 Figure 18.
PAGE 20
TDA7468 9 PACKAGE MECHANICAL DATA In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
PAGE 21
TDA7468 Figure 19. SO28 Mechanical Data & Package Dimensions mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S OUTLINE AND MECHANICAL DATA SO-28 8 ° (max.
PAGE 22
TDA7468 10 REVISION HISTORY Table 16.
PAGE 23
TDA7468 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.