Datasheet

TDA7419 I
2
C bus specification
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5 I
2
C bus specification
5.1 Interface protocol
The interface protocol comprises:
● a start condition (S)
● a chip address byte (the LSB determines read/write transmission)
● a subaddress byte
● a sequence of data (N-bytes + acknowledge)
● a stop condition (P)
● the max. clock speed is 500 kbits/s
● 3.3 V logic compatible
5.1.1 Receive mode
S = Start
R/W = "0" -> Receive Mode (Chip can be programmed by P)
"1" -> Transmission Mode (Data could be received by P)
ACK = Acknowledge
P = Stop
TS = Testing mode
AZ = AutoZero remain
AI = Auto increment
5.1.2 Transmission mode
SM = Soft-mute activated for main channel
X = Not Used
The transmitted data is automatic updated after each ACK. Transmission can be repeated
without new chip address.
5.1.3 Reset condition
A Power on reset is invoked if the supply voltage is below than 3.5 V. After that the following
data is written automatically into the registers of all subaddresses:
S 1 0 0 0 1 0 0 R/W ACK TS AZ AI A4 A3 A2 A1 A0 ACK DATA ACK P
S1000100R/WACKXXXXXXXSMACKP
MSB LSB
11111110