Datasheet

7/14
TDA7309
Figure 17. Acknowledge on the I
2
CBUS
Table 6. SDA, SCL I
2
CBUS Timing
All values referred to VIH min. and VIL max. levels
(*) Must be guaranteed by the I
2
C BUS master.
Figure 18. Definition of Timing on the I
2
C-bus
Symbol Parameter Min. Typ. Max. Unit
f
SCL
SCL clock frequency 0 400 kHz
t
BUF
Bus free time between a STOP and START condition 1.3 µs
t
HD:STA
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
0.6 µs
t
LOW
LOW period of the SCL clock 1.3 µs
t
HIGH
HIGH period of the SCL clock 0.6 µs
t
SU:STA
Set-up time for a repeated START condition 0.6 µs
t
HD:DA
Data hold time 0.300 µs
t
SU:DAT
Data set-up time 100 ns
t
R
Rise time of both SDA and SCL signals 20 300 ns (*)
t
F
Fall time of both SDA and SCL signals 20 300 ns (*)
t
SU:STO
Set-up time for STOP condition 0.6 µs
SCL
1
MSB
23789
SDA
START
ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
SDA
SCL
t
BUF
P S
t
HD;STA
t
LOW
t
R
t
F
t
HD;DAT
t
SU;DAT
t
HIGH
t
F
Sr P
t
SU;STA
t
HD;STA
t
SP
t
SU;STO
D95AU314
P = STOP
S = START