Datasheet

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1/14

TDA7309

March 2006

1FEATURES

■ INPUT MULTIPLEXER:

3 STEREO INPUTS

■ RECORD OUTPUT FUNCTION

■ LOUDNESS FUNCTION

■ VOLUME CONTROL IN 1dB STEPS

■ INDEPENDENT LEFT AND RIGHT VOLUME

CONTROL

■ SOFT MUTE FUNCTION

■ ALL FUNCTIONS PROGRAMMABLE VIA

SERIAL I

C BUS

2 DESCRIPTION

The TDA7309 is a control processor with indepen-

dent left and right volume control for quality audio

applications. Selectable external loudness and

soft mute functions are provided.

Control is accomplished by serial I

C bus micro-

processor interface.

The AC signal setting is obtained by resistor net-

works and switches combined with operational

amplifiers.

Thanks to the used BIPOLAR/CMOS Technology,

Low Distortion, Low Noise and Low DC stepping

are obtained.

DIGITAL CONTROLLED STEREO AUDIO PROCESSOR

WITH LOUDNESS

Figure 2. Block Diagram

INPUT

SELECTOR

LEFT

INPUTS

RIGHT

INPUTS

SUPPLY

16 7 15

VOLUME +

LOUDNESS

SOFT

MUTE

LOUD(L)

22µF

CREF

LOUD(R)

MUTE

OUT

LEFT

SCL

SDA

DIGGND

OUT

RIGHT

ADDR

D93AU045A

BUSSERIAL BUS DECODER + LATCHES

3 x

2.2µF

3 x

2.2µF

VOLUME +

LOUDNESS

AGNDV

3 CSM

100nF

TDA7309

Recout(R)

Recout(L)

Rev. 6

gure 1.

ages

Table 1. Order Codes

Part Number Package

TDA7309 DIP20

TDA7309D SO20

TDA7309D013TR Tape & Reel

DIP20

SO20

Summary of content (14 pages)

PAGE 1
TDA7309 DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS 1 FEATURES Figure 1. Packages ■ INPUT MULTIPLEXER: 3 STEREO INPUTS ■ RECORD OUTPUT FUNCTION ■ LOUDNESS FUNCTION ■ VOLUME CONTROL IN 1dB STEPS ■ INDEPENDENT LEFT AND RIGHT VOLUME CONTROL ■ SOFT MUTE FUNCTION ■ ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2C BUS 2 DIP20 SO20 Table 1. Order Codes DESCRIPTION The TDA7309 is a control processor with independent left and right volume control for quality audio applications.
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TDA7309 Figure 3. Pin Description RecoutL 1 20 IN3L OUTL 2 19 LOUDL CSM 3 18 IN2L SDA 4 17 IN1L SCL 5 16 VS DGND 6 15 CREF GND 7 14 IN1R ADD 8 13 IN2R OUTR 9 12 LOUDR 10 11 IN3R RecoutR D94AU058A Table 2. Absolute Maximum Ratings Symbol VS Parameter Value Unit 10.5 V –40 to 85 °C –55 to +150 °C Operating Supply Voltage Tamb Operating Ambient Temperature Tstg Storage Temperature Range Table 3. QUICK REFERENCE DATA Symbol Parameter Test Condition Min.
PAGE 3
TDA7309 Table 5. Electrical Characteristcs (Refer to the test circuit, Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 50Ω, all controls flat (G = 0), f = 1KHz unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit 5 (*) 9 10 V 7 10 mA 60 85 SUPPLY VS IS SVR Supply Voltage Supply Current Ripple Rejection dB INPUT SELECTORS RI Input Resistance 35 50 65 KΩ Sin Input Separation 80 90 dB 92 dB VOLUME CONTROL CRANGE Control Range AVMAX Max.
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TDA7309 Figure 5. Noise vs. Volume Setting. Figure 8. THD vs. RLOAD. Figure 6. SVRR vs. Frequency. Figure 9. Channel Separation vs. Frequency. Figure 7. THD vs. frequency Figure 10. Output Clip Level vs. Supply Voltage.
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TDA7309 Figure 11. Quiescen Current vs. Supply Voltage Figure 13. Loudness vs. Frequency (CLOAD = 100nF) vs. Volume Figure 12. Loudness vs. Volume Attenuation Figure 14. Loudness vs.
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TDA7309 3 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7313 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data Validity As shown in fig. 11, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.
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TDA7309 Figure 17. Acknowledge on the I2CBUS SCL 1 2 3 7 8 9 SDA MSB START ACKNOWLEDGMENT FROM RECEIVER D99AU1033 Table 6. SDA, SCL I2CBUS Timing Symbol Parameter Min. Typ. Max. Unit 400 kHz fSCL SCL clock frequency tBUF Bus free time between a STOP and START condition 1.3 µs Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.
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TDA7309 4 SOFTWARE SPECIFICATION 4.1 Interface Protocol The interface protocol comprises: ■ A start condition (s) ■ A chip address byte, containing the TDA7309 address (the 8th bit of the byte must be 0). The TDA7309 must always acknowledge at the end of each transmitted byte. ■ A sequence of data (N-bytes + acknowledge) ■ A stop condition (P) Figure 19. ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 400kbits/s Table 7.
PAGE 9
TDA7309 4.2 Power on reset condition 11111110 Table 10. Volume Codes MSB F6 F5 F4 F3 F2 F1 LSB 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 0 FUNCTION step 1dB 0 -7dB step 8dB 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 -40dB 0 1 1 0 -48dB 0 1 1 1 -56dB 1 0 0 0 -64dB 1 0 0 1 -72dB 1 0 1 0 -80dB 1 0 1 1 -88dB 1 1 X X MUTE Table 11.
PAGE 10
TDA7309 Table 12. Input Multiplexer Codes MSB F6 F5 1 0 1 F4 F3 F2 F1 LSB FUNCTION inputs X X X 0 0 MUTE X X X 0 1 IN2 X X X 1 0 IN3 X X X 1 1 IN1 Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
PAGE 11
TDA7309 Figure 20. DIP20 Mechanical Data & Package Dimensions mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L OUTLINE AND MECHANICAL DATA 3.3 0.130 DIP20 Z 1.34 0.
PAGE 12
TDA7309 Figure 21. SO20 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 12.60 13.00 0.496 0.512 E 7.40 7.60 0.291 0.299 e 1.27 0.050 H 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 k ddd OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.
PAGE 13
TDA7309 Table 13. Revision History Date Revision Description of Changes January 2004 5 First Issue in EDOCS DMS March 2006 6 Modified on the page 8/14 the “MAX CLOCK SPEED” to 400kbits/s.
PAGE 14
TDA7309 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.