Datasheet

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This is information on a product in full production.

October 2012 Doc ID 14134 Rev 7 1/25

STWD100

Watchdog timer circuit

Datasheet − production data

Features

■ Current consumption 13 µA typ.

■ Available watchdog timeout periods are

3.4 ms, 6.3 ms, 102 ms and 1.6 s

■ Chip enable input

■ Open drain or push-pull WDO output

■ Operating temperature range: –40 to +125 °C

■ Package SOT23-5, SC70-5 (SOT323-5)

■ ESD performance

– HBM: 2000 V

– RCDM: 1000 V

Applications

■ Telecommunications

■ Alarm systems

■ Industrial equipment

■ Networking

■ Medical equipment

■ UPS (uninterruptible power supply)

Table 1. Device summary

SOT23-5 (WY)

SC70-5,

SOT323-5 (W8)

Order code

Temperature

range

P a c k a g e P a c k i n g

Topside

marking

STWD100NYWY3F -40/+125 °C SOT23-5L Tape and reel WNY

STWD100YNYWY3F

(1)

1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC

Q001 and Q002 or equivalent are ongoing.

-40/+125 °C SOT23-5L (automotive grade) Tape and reel WYNY

STWD100NPWY3F -40/+125 °C SOT23-5L Tape and reel WNP

STWD100YNPWY3F

(1)

-40/+125 °C SOT23-5L (automotive grade) Tape and reel WYNP

STWD100PYW83F -40/+125 °C SOT323-5L Tape and reel WPY

www.st.com

Summary of content (25 pages)

PAGE 1
STWD100 Watchdog timer circuit Datasheet − production data Features ■ Current consumption 13 µA typ. ■ Available watchdog timeout periods are 3.4 ms, 6.3 ms, 102 ms and 1.
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Contents STWD100 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Watchdog input (WDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Watchdog output (WDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Chip enable input (EN) . . . . .
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STWD100 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SOT23-5 and SC70-5 (SOT323-5) pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures STWD100 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. 4/25 SOT23-5 and SC70-5 (SOT323-5) package connections . . . . . . . . Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open drain WDO output connection . . . . . . . . . . . . . . . . . . . . . . .
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STWD100 1 Description Description The STWD100 watchdog timer circuits are self-contained devices which prevent system failures that are caused by certain types of hardware errors (non-responding peripherals, bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.). The STWD100 watchdog timer has an input, WDI, and an output, WDO. The input is used to clear the internal watchdog timer periodically within the specified timeout period, twd.
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Description STWD100 Figure 2. Logic diagram VCC WDI STWD100 WDO EN GND AI12640a Note: WDO output is available in open drain or push-pull configuration. Figure 3. Block diagram 7$) 7$) TRANSITIONAL DETECTOR 7ATCHDOG TIMER /UTPUT TIMING 7$/ #,2 347$ X0 ONLY %. '.$ !) 6 Note: 6/25 Positive pulse on enable pin EN longer than 1 µs resets the watchdog timer.
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STWD100 2 Operation Operation The STWD100 device is used to detect an out-of-control MCU. The user has to ensure watchdog reset within the watchdog timeout period, otherwise the watchdog output is asserted and MCU is restarted. The STWD100 can be also enabled or disabled by the chip enable pin. 2.1 Watchdog input (WDI) The WDI input has to be toggled within the watchdog timeout period, tWD, otherwise the watchdog output, WDO, is asserted.
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Operation STWD100 Figure 4. Open drain WDO output connection 347$ 6 SYSTEM 6 6 6## 7$) 7$/ %. '.$ '.$ !) 6 2.3 Chip enable input (EN) All states mentioned in Section 2.1: Watchdog input (WDI) and Section 2.2: Watchdog output (WDO) are valid under the condition that EN is in logical low state. The behavior of EN is common to all versions (i.e. STWD100xP, STWD100xW, STWD100xX and STWD100xY).
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STWD100 Operation Figure 5. Interfacing to microprocessors with bidirectional reset I/O "UFFERED RESET TO OTHER SYSTEM COMPONENTS 6## 6## 347$ -ICROPROCESSOR 7$/ '.$ 234 '.
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Watchdog timing 3 Watchdog timing Figure 6. Power-up STWD100 0OWER UP WATCHDOG TIMER STARTS RUNNING AS SOON AS 6## RISES ABOVE ^ 6 ^ 6 6## !T POWER UP 7$) IS A DONgT CARE )T CAN BE OR #AN ALSO TRANSITION FROM HIGH TO LOW 7$) 8 IE OR BUT NOT FLOATING T 7$ "UT NO INPUT TRANSITION IS REQUIRED TO BEGIN TIMING 7$/ %.
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STWD100 Figure 7. Watchdog timing Normal triggering STWD100xP VCC Trigger only on rising edge. Falling edge is ignored. WDI tWD WDO EN X STWD100xW, STWD100xX, STWD100xY VCC Trigger on rising and falling edge of WDI.
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Watchdog timing Figure 8. STWD100 Timeout without re-trigger STWD100xP After a timeout and WDO is asserted, it will stay low for tWD time period, then return high. If no WDI trigger event occurs, WDO will again assert low after tWD time period. This cycle repeats until a WDI trigger event occurs. STWD100xW, STWD100xX, STWD100xY After a timeout and WDO is asserted, it will stay low for tPW time period, then return high. If no WDI trigger event occurs within tWD time period, WDO will again assert low.
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STWD100 Figure 9. Watchdog timing Trigger after timeout STWD100xP VCC If a WDI trigger occurs after the WDO output has asserted, the output will de-assert, but with a pulse width of at least 10 µs (min). WDI t WD WDO EN STWD100xW, STWD100xX, STWD100xY If a WDI trigger occurs after the WDO output has asserted, it is ignored, and the output remains asserted for the specified time, tPW. X >10 µs min. VCC Trigger ignored while WDO is low.
PAGE 14
Watchdog timing STWD100 Figure 10. Enable pin, EN, triggering STWD100xx ~ 2.2 V Whenever EN is high, all timing is reset, and the part is disabled. VCC Timing commences from 0 when EN goes low. WDI X (ie, 1 or 0 but not floating) WDO < tWD EN X tWD DISABLED STWD100xx VCC If EN goes high while WDO is asserted, WDO will de-assert but only after the nominal minimum pulse width of 10 µs has elapsed. WDI X (ie, 1 or 0 but not floating) tWD WDO tWD >10 µs min.
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STWD100 4 Maximum ratings Maximum ratings Stressing the device above the rating listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in Table 4 of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality documents. Table 3.
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DC and AC parameters 5 STWD100 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in Table 5 that follows, are derived from tests performed under the measurement conditions summarized in Table 4. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4.
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STWD100 DC and AC parameters Table 5. DC and AC characteristics Symbol Description Test condition(1) Min. Typ. Max. Unit 2.7 5 5.5 V 13 26 µA –1 +1 µA Input leakage current (WDI) –1 +1 µA VIH Input high voltage (WDI, EN) 0.7 VCC VIL Input low voltage (WDI, EN) VOL Output low voltage (WDO) VOH Output high voltage (WDO) (push-pull VCC ≥ 2.7 V, ISOURCE = 500 µA only) VCC ≥ 4.
PAGE 18
Package information 6 STWD100 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. The maximum ratings related to soldering conditions are also marked on the inner box label.
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STWD100 Package information Figure 11. SOT23-5 - 5-lead small outline transistor package outline Table 6. SOT23-5 - 5-lead small outline transistor package mechanical data Dimensions Symbol A mm inches Typ. Min. Max. Typ. Min. Max. 1.20 0.90 1.45 0.047 0.035 0.057 A1 0.15 0.006 A2 1.05 0.90 1.30 0.041 0.035 0.051 B 0.40 0.35 0.50 0.016 0.014 0.020 C 0.15 0.09 0.20 0.006 0.004 0.008 D 2.90 2.80 3.00 0.114 0.110 0.118 D1 1.90 E 2.80 0.102 0.118 e 0.
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Package information STWD100 Figure 12.
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STWD100 Package information Table 7. SC70 (SOT323-5) – 5-lead small outline transistor package mechanical data Dimensions Symbol mm Typ. inches Min. Max. A 0.80 A1 Min. Max. 1.10 0.031 0.043 0.00 0.10 0.000 0.004 0.80 1.00 0.031 0.039 b 0.15 0.30 0.006 0.012 c 0.10 0.22 0.004 0.009 A2 0.90 Typ. 0.035 D 2.00 1.80 2.20 0.079 0.071 0.087 E 2.10 1.80 2.40 0.083 0.071 0.094 E1 1.25 1.15 1.35 0.049 0.045 0.053 e 0.65 0.026 e1 1.30 0.051 L 0.36 0.
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Part numbering STWD100 7 Part numbering Table 8. Ordering information scheme Example: STWD100 Y N P WY Device type STWD100 Device grade Y: automotive grade Output type N: open drain (active low) P: push-pull (active low) Device version P: tWD = 3.4 ms, tPW = tWD = 3.4 ms W: tWD = 6.3 ms, tPW = 210 ms X: tWD = 102 ms, tPW = 210 ms Y: tWD = 1.
PAGE 23
STWD100 Package marking information 8 Package marking information Table 9. Device versions with marking descriptions Part number Watchdog timing period Output configuration Topside marking Bottomside marking(1) twd tpw STWD100NPxxxx 3.4 ms 3.4 ms Open drain WNP PYWW STWD100NWxxxx 6.3 ms 210 ms Open drain WNW PYWW STWD100NXxxxx 102 ms 210 ms Open drain WNX PYWW STWD100NYxxxx 1.6 s 210 ms Open drain WNY PYWW STWD100PWxxxx 6.
PAGE 24
Revision history 9 STWD100 Revision history Table 10. Document revision history Date Revision 08-Nov-2007 1 Initial release. 23-Jan-2008 2 Updated cover page and Table 5; document status upgraded to full datasheet. 28-Jan-2008 3 Updated cover page. 17-Mar-2008 4 Updated cover page, Figure 4, 7, 9, and Table 5, 9. 31-Jul-2008 5 Updated Features on cover page and Table 5. 6 Added product maturity information and section Applications, updated Section 1, Section 2.
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STWD100 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.