Datasheet

DocID13236 Rev 9 9/28

STVM100 Device operation

2.1.4 Data valid

The data on the SDA line must be stable during the high period of the clock. The high or low

state of the data line can only change when the clock signal on the SCL line is low (see

Figure 5). The data on the line may be changed during the clock signal low period. There is

one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition. The

number of data bytes transferred between the start and stop conditions is not limited. The

information is transmitted byte-wide and each receiver acknowledges transmission with a

ninth bit.

By definition, the device that gives out a message is called “transmitter”, the device that gets

the message is called “receiver”. The device that controls the message is called the

“master”. The devices controlled by the master are called “slave” devices.

Figure 5. Serial bus data transfer sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION

CHANGE OF

DATA ALLOWED

STOP

CONDITION