Datasheet

Device operation STVM100
8/28 DocID13236 Rev 9
2 Device operation
The STVM100 operates as a slave device on the serial bus. Access is obtained by
implementing a start condition, followed by the 7-bit slave address (1001111), and the eighth
bit for READ/WRITE identification. The volatile DAC register and non-volatile EEPROM
values can be read out or written in.
2.1 2-wire bus characteristics and conditions
This bus is intended for communication between different ICs. It consists of two lines:
• a bi-directional data signal (SDA).
• a clock signal (SCL).
The SDA and SCL lines must be connected to a positive supply voltage via a pull-up
resistor. The following protocols have been defined:
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high.
• Changes in the data line while the clock line is high will be interpreted as control
signals.
2.1.1 Bus not busy
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the data line state from high-to-low while the clock is high indicate the start
condition.
2.1.3 Stop data transfer
A change in the data line state from low-to-high while the clock is high indicates the stop
condition.