Datasheet

STULPI01A, STULPI01B Bump configuration
Doc ID 14817 Rev 4 7/44
2 Bump configuration
Figure 2. Pin connections
µTFBGA36 (bottom view)
A
B
C
D
E
F
1 2 3 4 5 6
µTFBGA36 (through top side view)
654321
D5D4CLKD3D2D1A
D6
1V8
VIO
GND
1V8
VIO
1V8
VIO
D0B
D7
GND
RESETn
CSn/
PWRDN
RREFDMC
STPNXTPSWnID
GNDDPD
1V2VDIRGND3V3V
VB_REF
_FAULT
GNDE
XOXIVBUSVBATNCNCF
654321
D
5
D5
D
4
D4
C
L
K
CLK
D
3
D3
D
2
D2
D
1
D1A
D
6
D6
GND
V
DVIO
D
0
D0B
D
7
D7GND
R
E
SE
T
n
RESETn
C
S
n/
P
W
R
D
N
CSn/
PWRDN
RR
E
FRREFD
M
DMC
S
T
P
STP
N
X
T
NXT
P
S
Wn
PSWn
I
D
IDGND
D
P
DPD
1V2V
D
I
R
DIRGND3V3V
V
B
_
R
E
F
_
F
A
U
LT
VB_REF
_FAULT
GNDE
XOXI
V
B
U
S
T
VBUSVBATNCNCF
AM04945v1
V
DVIO
V
DVIO
Table 2. Pinout and bump description
Bump Symbol Type Description
B1 D0 I/O Data bit [0] (V
DVIO
referred). UART TXD signal.
A1 D1 I/O Data bit [1] (V
DVIO
referred). UART RXD signal.
A2 D2 I/O Data bit [2] (V
DVIO
referred). UART reserved pin.
A3 D3 I/O Data bit [3] (V
DVIO
referred). UART active high interrupt indication.
A4 CLK O Clock out (V
DVIO
referred)
A5 D4 I/O Data bit [4] (V
DVIO
referred)
A6 D5 I/O Data bit [5] (V
DVIO
referred)
B6 D6 I/O Data bit [6] (V
DVIO
referred)
C6 D7 I/O Data bit [7] (V
DVIO
referred)
D6 STP I ULPI stop signal (V
DVIO
referred)
D5 NXT O ULPI next signal (V
DVIO
referred)
E5 DIR O ULPI direction signal (V
DVIO
referred)
C3 CSn/PWRDN I Chip select active low, power-down active high
C4 RESETn I Active low asynchronous reset
D1 DP I/O Positive data line of the USB. 5 V tolerant.
C1 DM I/O Negative data line of the USB. 5 V tolerant.
D3 ID I ID pin of the USB connector for initial device role selection. 5 V tolerant.
F4 VBUS I/O V
BUS
line of the USB interface, requires an external capacitor of 4.7 µF.