Datasheet

STULPI01A, STULPI01B ULPI registers
Doc ID 14817 Rev 4 37/44
Note: Address 14h(Read-only with auto-clear).
These bits are set by the STULPI01 when an unmasked change occurs on the
corresponding internal signal. The STULPI01 automatically clears all bits when the link
reads this register, or when Low-power mode is entered. The STULPI01 also clears this
register when Serial mode or Car Kit mode is entered regardless of the value of
ClockSuspendM. The interrupt circuitry is powered down in any mode when both rising and
falling edge enables are disabled. To ensure the interrupts are detectable when the clock is
powered down, the link should enable both rising and falling edges.
The STULPI01 follows the rules in Tabl e 2 0 for setting any latch register bit. It is important to
note that if the register read data is returned to the link in the same cycle that a USB
interrupt latch bit is to be set, the interrupt condition is given immediately in the register read
data and the latch bit is not set.
Note that it is optional for the link to read the USB interrupt latch register in Synchronous
mode because the RX CMD byte already indicates the interrupt source directly.
Table 23. USB interrupt latch register
Field name Bits Access Reset Description
Host disconnect
latch
0rd 0b
Set to 1b by the STULPI01 when an unmasked event occurs on
host disconnect. Cleared when this register is read. Applicable
only in Host mode.
VbusValid latch 1rd 0b
Set to 1b by the STULPI01 when an unmasked event occurs on
VbusValid. Cleared when this register is read.
SessValid latch 2rd 0b
Set to 1b by the STULPI01 when an unmasked event occurs on
SessValid. Cleared when this register is read. SessValid is the
same as UTMI+AValid.
SessEnd latch 3rd 0b
Set to 1b by the STULPI01 when an unmasked event occurs on
SessEnd. Cleared when this register is read.
ID latch 4rd 0b
Set to 1b by the STULPI01 when an unmasked event occurs on
ID. Cleared when this register is read. ID is valid 50 ms after ID
is set to 1b, otherwise ID is undefined and should be ignored.
Reserved 7:5 rd 0b Reserved
Table 24. Setting rules for interrupt latch register
Input conditions
Resultant value of latch register bit
Register read data returned in
current clock cycle
Interrupt latch bit is to be set in
current clock cycle
No No 0
No Yes 1
Ye s N o 0
Ye s Yes 0