Datasheet

ULPI registers STULPI01A, STULPI01B
30/44 Doc ID 14817 Rev 4
8 ULPI registers
Table 13. ULPI register map overview
Field name Size (bits)
Address (6 bits)
Rd Wr Set Clr
Immediate register set
Vendor ID low 8 00h - - -
Vendor ID high 8 01h - - -
Product ID low 8 02h - - -
Product ID high 8 03h - - -
Function control 8 04-06h 04h 05h 06h
Interface control 8 07-09h 07h 08h 09h
OTG control 8 0A-0Ch 0Ah 0Bh 0Ch
USB interrupt enable rising 8 0D-0Fh 0Dh 0Eh 0Fh
USB interrupt enable falling 8 10-12h 10h 11h 12h
USB interrupt status register 8 13h - - -
USB interrupt latch register 8 14h - - -
Debug 8 15h - - -
Scratch 8 16-18h 16h 17h 18h
Car kit control register 8 16-1Bh 19h 1Ah 1Bh
Reserved 8 1C-2Eh
Access extended register set (see Table 14)8-2Fh--
Reserved 8 30-3Ch
Power control 3D-3Fh
Extended register set Address (8 bits)
Maps to immediate register set above 8 00-3Fh
Reserved 8 40-FFh
Table 14. Register access legend
Access code Expanded name Meaning
rd Read Register can be read. Read-only if this is the only mode given.
wr Write Pattern on the data bus is written over all bits of the register.
sSet
Pattern on the data bus is OR’d with the register value and written into
the register.
c Clear
Pattern on the data bus is a mask. If a bit in the mask is set, then the
corresponding register bit is set to zero (cleared).