Datasheet

STULPI01A, STULPI01B Block description
Doc ID 14817 Rev 4 25/44
Note: Software reset is not required in the startup procedure for the STULPI. The chip is ready for
operation after the hardware reset procedure.
6.18.7 High-speed mode entry
In High-speed mode, the internal 480-MHz clock is generated by the DLL, which must be
calibrated any time the device enters High-speed mode by writing '00' to the XcvrSel field in
the Function Control register. During the DLL calibration, it is not possible to accept any
commands, therefore, to avoid any communication problems with the controller, the clock on
the ULPI interface is stopped. See Figure 10 for more information.
Figure 8. Startup sequence