Datasheet

Electrical characteristics STULPI01A, STULPI01B
14/44 Doc ID 14817 Rev 4
Table 7. Switching characteristics
Symbol Parameter Test conditions
(1)
Min. Typ. Max. Unit
Reset
t
RESETEXT
Width of reset pulse on RESETn pin 10 µs
UART mode
t
RISE
Switching time (max. low to min.
high)
C
LOAD
= 185 pF 215 ns
t
FAL L
Switching time (min. high to max.
low)
C
LOAD
= 185 pF 215 ns
t
PD_RX
Delay time (50% DM to 50% D1) C
L
= 10 pF 60 ns
t
PD_TX
Delay time (50% D0 to 50% DP) 60 ns
t
UARTON2V7
Turn-on time for TXD line (2V7)
UART_2V7 = 1 measured
from DIR assertion
22.5ms
t
UARTOFF2V7
Turn-off time for TXD line (2V7)
UART_2V7 = 1 measured
from STP assertion
1µs
t
UARTON
Turn-on time for TXD line
UART_2V7 = 0 measured
from DIR assertion
60 ns
t
UARTOFF
Turn-off time for TXD line
UART_2V7 = 0 measured
from DIR de-assertion
60 ns
Low-speed driver
t
LR
Data signal rise time C
LOAD
= 600 pF 75 100 300 ns
t
LF
Data signal fall time C
LOAD
= 600 pF 75 100 300 ns
RFM
LS
Rise and fall time matching -20 20 %
DR
LS
Low-speed data rate 1.49925 1.50075 Mb/s
t
DDJ1
Data jitter to next transition Includes freq. tolerances -25 25 ns
t
DDJ2
Data jitter for paired transitions Includes freq. tolerances -14 14 ns
t
LEOPT
SE0 interval of EOP 1250 1500 ns
Full-speed driver
t
FR
Data signal rise time C
LOAD
= 50 pF 4 20 ns
t
FF
Data signal fall time C
LOAD
= 50 pF 4 20 ns
RFM
FS
Rise and fall time matching -10 +10 %
DR
HS
Full-speed data rate 11.994 12.006 Mb/s
t
DJ1
Data jitter to next transition Includes freq. tolerances -3.5 3.5 ns
t
DJ2
Data jitter for paired transitions Includes freq. tolerances -4 4 ns
t
FEOPT
SE0 interval of EOP 160 175 ns
Clock generation constants
t
PLL
PLL lock time
(2)
200 µs
t
DLL
DLL lock time
(2)
280 µs