STULPI01A, STULPI01B High-speed USB On-The-Go ULPI transceiver Datasheet − production data Features ■ USB-IF high-speed certified to the universal serial bus specification rev. 2.0 ■ Meets the requirements of the universal serial bus specification rev. 2.0, On-The-Go supplement to the USB 2.0 specification 1.0a and ULPI transceiver specification 1.1 ■ Standard ULPI (UTMI+ low pin interface) 1.1 digital interface ■ Fully compliant with ULPI 1.
Contents STULPI01A, STULPI01B Contents 1 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Bump configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Timing diagram . . . . . . . . . . . .
STULPI01A, STULPI01B Contents 6.17 VIO OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18 Startup procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18.1 ULPI device detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18.2 SDR mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18.3 External clock detection . .
List of tables STULPI01A, STULPI01B List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. 4/44 Bill of materials - external components . . . . . . . . . . . . . . . . . . . . . . . Pinout and bump description . . . . . . . . . . . . . . . . . . .
STULPI01A, STULPI01B List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Peripheral only, configuration with external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 High-speed driver eye pattern . . . . . . . . . . . . . .
Application diagrams STULPI01A, STULPI01B 1 Application diagrams Figure 1. Peripheral only, configuration with external clock C C F2 F3 CF4 VDVIO 3V3V 1V2V Battery voltage VBAT VDVIO XI VDVIO XO CF4 High-speed USB-OTG controller CLK DIR STP NXT open External clock or ground 19.2/26 MHz VDVIO amplitutde Mini-B ID DP DM VBUS RBUS D[0]...D[7] C D+ DVBUS GND T RREF RESETn CSn / PWRDN RREF E2 E1 PSWn GND CF1 VB_REF_FAULT 5x GND AM04944v2 Table 1.
STULPI01A, STULPI01B Bump configuration 2 Bump configuration Figure 2. Pin connections 1 2 3 4 5 6 F NC NC VBAT T VBUS E GND VB_REF _FAULT 3V3V D DP GND ID C DM RREF B D0 1V8 V DVIO VIO A D1 D2 1 2 XI XO GND DIR 1V2V PSWn NXT STP GND D7 A B C D E F CSn/ RESETn PWRDN V1V8 DVIO VIO GND GND V1V8 DVIO VIO D6 D3 CLK D4 D5 4 5 6 3 µTFBGA36 (bottom view) µTFBGA36 (through top side view) AM04945v1 Table 2.
Bump configuration Table 2. STULPI01A, STULPI01B Pinout and bump description (continued) Bump Symbol F1 NC Not connected F2 NC Not connected. E2 VB_REF_FAULT I Voltage reference for internal OC detector input or digital input from external OC detector (V3V3V referred). 5 V tolerant. D4 PSWn O External charge pump control, active low. 5 V tolerant, open drain. F5 XI I External clock input (VDVIO referred). F6 XO O XO pin must be left floating or grounded (crystal is not supported).
STULPI01A, STULPI01B Maximum ratings 3 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VDVIO Digital I/O supply voltage -0.3 to +4.0 V V1V2 Digital core supply voltage (provided internally by LDO) -0.3 to +1.4 V V3V3 Analog supply voltage (provided internally by LDO) -0.3 to +4.0 V VBAT Battery supply voltage -0.3 to +7.0 V DC voltage on digital pins (CLK, DIR, STP, NXT, D[0-7], RESETn, XI, CSn/PWRDN) -0.3 to +4.
Electrical characteristics STULPI01A, STULPI01B 4 Electrical characteristics Table 6. Electrical characteristics Symbol Parameter Test conditions(1) Min. Typ. Max.
STULPI01A, STULPI01B Table 6. Electrical characteristics Electrical characteristics (continued) Symbol IIL Parameter Test conditions Min. Typ. Low level input leakage curVIL = 0.2 V rent Max. Unit ±1.0 µA VPDH High level input voltage (CSn/PWRDN pin) VBAT = 3.0 V to 4.5 V VPDL Low level input voltage (CSn/PWRDN pin) VBAT = 3.0 V to 4.5 V 0.4 V IPDH High level input leakage current (CSn/PWRDN pin) VPD = 1.4 V, VBAT = 4.5 V ±1.
Electrical characteristics Table 6. STULPI01A, STULPI01B Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit 20 45 95 mV Overcurrent detector VOC Overcurrent trip threshold VB_REF_FAULT – VBUS VOC = VB_REF_FAULT – VBUS ID pin pull-up current VID = 0 V ID IID_PU RID_GND ID line short resistance to detect ID GND state RID_FLOAT ID line short resistance to detect ID FLOAT state 70 µA 1 kΩ 100 kΩ VDVIO - 0.15 V UART mode (2.
STULPI01A, STULPI01B Table 6. Electrical characteristics Electrical characteristics (continued) Symbol Parameter VHSDNJ HS data DN J state level VHSDNK HS data DN K state level VCHIRPJ Chirp J level (differential voltage) VCHIRPK Chirp K level (differential voltage Test conditions (2) (2) Min. Typ. Max. Unit 380 440 mV -10 10 mV 700 1100 mV -900 -500 mV Full-speed/Low-speed receivers VDI VSE_TH Diff.
Electrical characteristics Table 7. STULPI01A, STULPI01B Switching characteristics Symbol Test conditions(1) Parameter Min. Typ. Max. Unit Reset tRESETEXT Width of reset pulse on RESETn pin 10 µs UART mode tRISE Switching time (max. low to min. high) CLOAD = 185 pF 215 ns tFALL Switching time (min. high to max. low) CLOAD = 185 pF 215 ns tPD_RX Delay time (50% DM to 50% D1) CL = 10 pF 60 ns tPD_TX Delay time (50% D0 to 50% DP) 60 ns 2.
STULPI01A, STULPI01B Table 7. Electrical characteristics Switching characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit High-speed driver tHSR Data rise time 500 ps tHSF Data fall time 500 ps Waveform requirements including jitter DRHS Specified by eye pattern (Figure 3) High-speed data rate 479.76 480.
Electrical characteristics Figure 3. STULPI01A, STULPI01B High-speed driver eye pattern Level 1 Point 3 +400 mV differential Point 4 Point 1 0V differential Point 2 Point 5 Point 6 -400 mV differential Level 2 0% Unit interval 100 % AM04946v2 Table 8.
STULPI01A, STULPI01B Timing diagram 5 Timing diagram Figure 4. Rise and fall time tR tF VOH_DRV 90% 90% 10% VOL_DRV 10% CS26080 Figure 5. Simplified block diagram ID VBUS VB_REF_FAULT PSWn RESETn XI XO Oscillator and PLL OTG block Block Overcurrent fault detector Charge pump, Pump, VBUS comparators Comparators ID Detector detector VDVIO Power on reset GND CLK DIR STP NXT ULPI ULPI UTMI + UTMI + interface Interface Core core wrapper USB 2.
Block description 6 STULPI01A, STULPI01B Block description The STULPI01 integrates a comparator for the VBUS, ID line detector, differential HS data driver, differential and single-ended receivers, low dropout voltage regulators, and control logic. The STULPI01 provides a complete solution for the connection of a digital USB host/device/OTG controller to a USB bus. 6.1 Oscillator and PLL An external clock (digital square wave VDVIO referred) driven into XI must be used (version STULPI01A or STULPI01B).
STULPI01A, STULPI01B 6.6 Block description External charge pump It is possible to use an external charge pump or power switch controlled by the PSWn pin (active low open drain). This functionality is controlled by DrvVbus and DrvVbusExternal ULPI OTG control register bits. 6.7 VBUS comparators and VBUS overcurrent (OC) detector These comparators monitor the VBUS voltage. VBUS valid status signals that the voltage is above the VBUS_VLD level (4.4 V).
Block description Figure 6. STULPI01A, STULPI01B VB_REF_FAULT pin functionality VBUS VBUS VBUSVLD + Internal VBUS Valid [0,X] REF - VBOC + VBREF RX CMD VBUS Valid [1,0] VBUS VBREF_FAULT 0 [1,1] /EN 1 2 EN RIN_VBREF FAULT [UseExternalVbusIndicator, IndicatorPassthru] Schmitt (5 V TOLERANT) OverCurrent_PD or neg (UseExternalVbusIndicator) IndicatorComplement Table 9.
STULPI01A, STULPI01B Block description and sensing. The digital part consists of a serializer and deserializer, transforming serial bit stream to 8-bit parallel port, and finite state machine implementing the PHY protocol layer, bit stuffing, unstuffing, etc. Figure 7. USB 2.0 PHY block diagram 3.3 V HS Ser-Des LS/FS Ser-Des DP 3.3 V DN HS Disconnect Det. Squelch Detector LS/FS SE Receivers 19.25 kΩ AM04949v2 6.
Block description 6.14 STULPI01A, STULPI01B Car Kit (UART) mode This mode is entered by writing to the Car Kit mode bit in the interface control register. The STULPI01 does not implement all features of Car Kit mode, only the UART functionality is preserved. Table 10.
STULPI01A, STULPI01B Table 11. Block description Low-power mode Signal Map to Dir Description Linestate (0) D0 out Driven combinatorially from SE receivers Linestate (1) D1 out Driven combinatorially from SE receivers Reserved D2 out Reserved INT D3 out Active high interrupt indication. Asserted whenever any unmasked interrupt occurs. Low-power mode is exited by asserting the STP pin high.
Block description STULPI01A, STULPI01B Note: IMPORTANT: The controller must not drive the DATA lines to a value other than 0x00 or 0x01 during the first rising edge of ULPI CLK, otherwise the behavior of the device may be undefined. 6.18.3 External clock detection The square wave clock can be applied to the oscillator input. The input square wave clock amplitude is referenced to VDVIO. The XO pin can be left floating or grounded. 6.18.4 Reset behavior A typical startup sequence is shown in Figure 12.
STULPI01A, STULPI01B Block description Note: Software reset is not required in the startup procedure for the STULPI. The chip is ready for operation after the hardware reset procedure. 6.18.7 High-speed mode entry In High-speed mode, the internal 480-MHz clock is generated by the DLL, which must be calibrated any time the device enters High-speed mode by writing '00' to the XcvrSel field in the Function Control register.
Block description Figure 9. STULPI01A, STULPI01B RESETn behavior AM04951v1 Figure 10.
STULPI01A, STULPI01B Block description Figure 11. UART mode entry (2.7 V) Figure 12. UART mode exit (2.
State transitions 7 State transitions Table 12.
STULPI01A, STULPI01B Table 12.
ULPI registers STULPI01A, STULPI01B 8 ULPI registers Table 13.
STULPI01A, STULPI01B Table 15. ULPI registers Vendor and product ID Register Bits Access Address Value Description VENDOR_ID_LOW 7:0 rd 00h 83 h Lower byte of vendor ID. VENDOR_ID_HIGH 7:0 rd 01h 04 h Upper byte of vendor ID. PRODUCT_ID_LOW 7:0 rd 02h 4b h Lower byte of product ID number. PRODUCT_ID_HIGH 7:0 rd 03h 4f h Upper byte of product ID number. Table 16. Power control register Field name Bits Access Reset Reserved 0 rd/wr/s/c 0b Reserved.
ULPI registers Table 17. Field name XcvrSelect TermSelect OpMode Reset STULPI01A, STULPI01B Function control register Bits 1:0 2 4:3 5 Access rd/wr/s/c rd/wr/s/c rd/wr/s/c rd/wr/s/c Reset Description 01b Selects the required transceiver speed.
STULPI01A, STULPI01B Table 18. ULPI registers Interface control register Field name 6-pin FsLsSerialMode 3-pin FsLsSerialMode Carkit mode Bits 0 1 2 Access rd/wr/s/c rd/wr/s/c rd/wr/s/c Reset Description 0b Changes the ULPI interface to 6-pin Serial mode. The STULPI01 automatically clears this bit when Serial mode is exited. 0b: FS/LS packets are sent using parallel interface. 1b: FS/LS packets are sent using 6-pin serial interface. 0b Changes the ULPI interface to 3-pin Serial mode.
ULPI registers Table 19. STULPI01A, STULPI01B OTG control register Field name Bits Access Reset Description IdPullup 0 rd/wr/s/c 0b Connects a pull-up to the ID line and enables sampling of the signal level. 0b: disables sampling of ID line. 1b: enables sampling of ID line. DpPulldown 1 rd/wr/s/c 1b Enables the 15 kΩ pull-down resistor on DP. 0b: pull-down resistor not connected to DP. 1b: pull-down resistor connected to DP.
STULPI01A, STULPI01B Table 20. ULPI registers USB interrupt enable rising register Field name Bits Access Reset Description Host disconnect rise 0 rd/wr/s/c 1b Generates an interrupt event notification when host disconnect changes from low to high. Applicable only in Host mode (DpPulldown and DmPulldown both set to 1b). VbusValid rise 1 rd/wr/s/c 1b Generates an interrupt event notification when VbusValid changes from low to high.
ULPI registers Table 21. STULPI01A, STULPI01B USB interrupt enable falling register Field name Bits Access Reset Host disconnect fall 0 rd/wr/s/c 1b Generates an interrupt event notification when the host disconnect changes from high to low. Applicable only in Host mode. VbusValid fall 1 rd/wr/s/c 1b Generates an interrupt event notification when VbusValid changes from high to low.
STULPI01A, STULPI01B Table 23. ULPI registers USB interrupt latch register Field name Bits Access Reset Description Host disconnect latch 0 rd 0b Set to 1b by the STULPI01 when an unmasked event occurs on host disconnect. Cleared when this register is read. Applicable only in Host mode. VbusValid latch 1 rd 0b Set to 1b by the STULPI01 when an unmasked event occurs on VbusValid. Cleared when this register is read.
ULPI registers Table 25. STULPI01A, STULPI01B Debug register Field name Bits Access Reset Description LineState0 0 rd 0b Contains the current value of LineState(0) LineState1 1 rd 0b Contains the current value of LineState(1) Reserved 7:2 rd 0b Reserved Note: Address 15h(Read-only) indicates the current value of various signals useful for debugging. Table 26.
STULPI01A, STULPI01B 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
Package mechanical data STULPI01A, STULPI01B Figure 13. µTFBGA36 package outline " Table 28. µTFBGA36 mechanical data Dimensions Symbol mm . Min. Typ. Max. Min. Typ. Max. A 0.93 1.1 1.11 36.6 3.3 43.7 A1 0.15 0.25 5.9 9.8 A2 0.78 0.86 30.7 33.9 b 0.25 0.30 0.35 9.8 11.8 13.8 D 3.5 3.6 3.7 137.8 141.7 145.7 D1 E 40/44 mils. 2.5 3.5 3.6 98.4 3.7 137.8 141.7 E1 2.5 98.4 e 0.5 19.7 F 0 .55 21 .7 Doc ID 14817 Rev 4 145.
STULPI01A, STULPI01B Package mechanical data Figure 14. Tape and reel µTFBGA36 package outline 4A2 4&"'! 1. Drawing not to scale. Table 29. Tape and reel µTFBGA36 mechanical data Dimensions mm. Symbol Min. Typ. A inch. Max. Min. Typ. 330 13.2 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T Max. 0.504 0.519 14.4 0.567 Ao 3.9 0.154 Bo 3.9 0.154 Ko 1.50 0.059 Po 3.9 4.1 0.154 0.161 P 7.9 8.1 0.311 0.
Order codes STULPI01A, STULPI01B 10 Order codes Table 30. Order codes Order code STULPI01ATBR(1) Key differences Package Packaging fOSC = 19.2 MHz, CSn/PWRDN = 0 “ON” µTFBGA36 (3.6 x 3.6 mm typ.) 3000 parts per reel STULPI01BTBR(1) fOSC = 26 MHz, CSn/PWRDN = 0 “ON” µTFBGA36 (3.6 x 3.6 mm typ.) 3000 parts per reel 1. All these versions need a digital external clock on the XI pin; the XO pin must be left floating or grounded (crystal is not supported).
STULPI01A, STULPI01B Revision history 11 Revision history Table 31. Document revision history Date Revision Changes 20-Jun-2008 1 First release. 24-Sep-2010 2 Replaced “IV8VIO” with “DVIO” throughout datasheet; updated Table 2, 3, 5, 7; updated ECOPACK® text in Section 9; reformatted document, minor textual changes. 26-Jan-2011 3 Updated Table 2, 3, 12; updated pin name to VDVIO throughout document; minor formatting changes.
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