Datasheet

Pin configuration STSMIA832
8/25 Doc ID 12174 Rev 5
In the beginning of frame and in the end of frame, line synchronization codes are replaced
by the frame synchronization codes. Synchronization signal usage is shown in figure 7
below. Bit order of the synchronization codes is the same as for data, byte-wise LSB first.
The purpose of logical channels is to separate different data flows, which are interleaved in
the data stream.
The DMA channel identifier number is directly encoded in the 4-byte CCP embedded sync
codes. The CCP receiver will monitor the DMA channel identifier and de-multiplex the
interleaved video streams to their appropriate DMA channel. A maximum of 8 data streams
is supported. Valid channel identifiers are 0 to 7.
Figure 7. CCP2 synchronization codes
Table 2. Synchronization codes as per SMIA specifications
(1)
Name Synchronization codes Notes
SOL FFH 00H 00H X0H Line Start Code
EOL FFH 00H 00H X1H Line End Code
SOF FFH 00H 00H X2H Frame Start Code
EOF FFH 00H 00H X3H Frame End Code
Logical Channels FFH 00H 00H 0XH (to) FFH 00H 00H 7XH DMA Channel Identifier from Channel 0 to 7
1. X = channel number 0 to 7.