Datasheet

STSMIA832 Timing diagram
Doc ID 12174 Rev 5 19/25
Note: DATA_IN and STROBE are the input signals, CLKH is an internal signal i.e internal
extracted clock having half frequency respect to the external clock. All others are output
signals.
Figure 14. Enabled sync mode (SYNC_SEL = VDD) (D1-D8 will transmit the input data DIN,
excluding SYNC CODE) and CLASS_SEL = V
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