Datasheet

Timing diagram STSMIA832
18/25 Doc ID 12174 Rev 5
7 Timing diagram
Unless otherwise specified T
A
= 25°C.
Note: DATA_IN and STROBE are the input signals, CLKH is an internal signal i.e internal
extracted clock having half frequency respect to the external clock. All others are output
signals.
Figure 13. Disabled sync mode (SYNC_SEL = GND) (D1-D8 will transmit the input data DIN,
including SYNC CODE) and CLASS_SEL = V
L