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May 2010 Doc ID 12174 Rev 5 1/25

STSMIA832

1.8 V / 2.8 V high speed dual differential line receivers,

standard mobile imaging architecture (SMIA) decoder deserializer

Features

■ Sub-low voltage differential signaling inputs:

= 100 mV min. with R

= 100 Ω, C

= 10 pF

■ High signaling rate:

= 650 Mbps max (D+,D-,STRB+,STRB-)

OUT

= 82 MHz max (CLK)

OUT

= 82 Mbps max (for each data line D1-D8)

■ Very high speed strobe to clock:

PLH

~ t

PHL

= 5.2 ns (typ) at V

= 2.8 V;

= 1.8 V

■ Operating voltage range:

(OPR) = 2.65 V to 3.6 V

(OPR) = 1.65 V to 1.95 V

■ Symmetrical output impedance

(D1-D8, H-SYNC, V-SYNC, CLK):

I = I

= 4 mA (min) at V

= 2.65 V;

= 1.8 V

■ Low power dissipation (disabled: EN = gnd):

SOFF

= I

+ I

= 10 µA (Max)

■ SMIA specification compliant

■ Support for SMIA CCP RAW8, RAW10 and

RAW12 8-bit packet

■ CLASS 0 and CLASS 1, 2 supported (config.

by CLASS_SEL)

■ CMOS logic input threshold

(EN, SYNC_SEL, CLASS_SEL):

= 0.3 x V

; V

= 1.65 V to 1.95 V

= 0.7 x V

; V

= 1.65 V to 1.95 V

■ 3.6 V tolerant on inputs

(EN, SYNC_SEL, CLASS_SEL)

■ 32 BIT synchronization codes (SOF, EOF,

SOL, EOL)

■ Leadfree TFBGA package

(RoHS restriction of hazardous substances)

Applications

■ Feature phone (Mid-end 2 - 8 MPixel)

■ PDA, digital camera

■ Notebook, eBook (webcam), UMPC, MID

Description

The STSMIA832 receiver converts the subLVDS

clock/datastream (up to 650 Mbps throughput

bandwidth) back into parallel 8 bits of

CMOS/LVTTL. The device recognizes the SMIA

32 bit start of frame (SOF), end of frame (EOF),

start of line (SOL) and end of line (EOL)

sequences to generate the H-SYNC and V-SYNC

signals. Output LVTTL clock (up to 82 MHz) is

transmitted in parallel with data. Output data are

rising-edge strobes. This chipset is an ideal

means to link mobile camera modules to

Baseband processors. In order to minimize static

current consumption, it is possible to shut down

the device when the interface is not being used by

a power-down (EN) pin that reduces the

maximum current consumption to 10 µA making

this device ideal for portable applications like

mobile phone and portable battery equipment. A

configurable input (Class_Sel) is provided to

select different CLASS (0 or 1, 2) mode inside the

SMIA standard specifications.

The STSMIA832 is offered in a TFBGA package

to optimize PCB space. All inputs and outputs are

equipped with protection circuits against static

discharge, giving them ESD immunity from

transient excess voltage. The STSMIA832 is

characterized for operation over the commercial

temperature range - 40 °C to 85 °C.

TFBGA25

www.st.com

Summary of content (25 pages)

PAGE 1
STSMIA832 1.8 V / 2.8 V high speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer Features ■ Sub-low voltage differential signaling inputs: VID = 100 mV min. with RT = 100 Ω, CL = 10 pF ■ High signaling rate: fIN = 650 Mbps max (D+,D-,STRB+,STRB-) fOUT = 82 MHz max (CLK) fOUT = 82 Mbps max (for each data line D1-D8) ■ Very high speed strobe to clock: tPLH ~ tPHL = 5.2 ns (typ) at VDD = 2.8 V; VL = 1.8 V ■ Operating voltage range: VDD(OPR) = 2.
PAGE 2
Contents STSMIA832 Contents 1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 2.1 Pin descriptions for reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Supplementary notes: SMIA specification . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information . . . . . . . . . . . . . . .
PAGE 3
STSMIA832 Schematic diagram 1 Schematic diagram Figure 1. Simplified application block diagram Figure 2.
PAGE 4
Pin configuration STSMIA832 2 Pin configuration Figure 3. Pin connections (top through view - bumps are on the other side) Table 1.
PAGE 5
STSMIA832 2.1 Pin configuration Pin descriptions for reference: (D+, D-, STRB+, STRB-) Differential subLVDS data and strobe inputs to the receiver from the camera sensor interface. The signals operate at 150 mV typical differential voltage levels and a common mode voltage of 900 mV. The operating data rate is 650 Mbps maximum. Depending on the CLASS_SEL pin selection mode, Data/Clock signaling or Data/Strobe signaling modes are activated. D1-D8, CLK STSMIA832 output data and clock lines.
PAGE 6
Pin configuration STSMIA832 VDD, VL Both the camera sensor module and the baseband processor interface operate at VL = 1.8 V. The subLVDS receiver core operating voltage is VDD = 2.8 V typical. 2.2 Supplementary notes: SMIA specification The standard mobile imaging architecture (SMIA) specification defines an interface between the digital camera module and mobile phone engine.
PAGE 7
STSMIA832 Figure 5. Pin configuration Data-strobe signaling Data is sent byte-wise LSB first. The state of the data and strobe signals at the beginning of transmission are fixed i.e. the state of data is logic high and the state of strobe is logic low. The number of clock cycles between synchronization codes has to be even, both between SOL (or SOF) – EOL (or EOF) and EOL (or EOF) – SOL (or SOF).
PAGE 8
Pin configuration STSMIA832 In the beginning of frame and in the end of frame, line synchronization codes are replaced by the frame synchronization codes. Synchronization signal usage is shown in figure 7 below. Bit order of the synchronization codes is the same as for data, byte-wise LSB first. Figure 7. CCP2 synchronization codes The purpose of logical channels is to separate different data flows, which are interleaved in the data stream.
PAGE 9
STSMIA832 Application information 3 Application information 3.1 Inputs Technological advancements in deeper submicron processes have lowered the supply voltage levels of semiconductor devices, creating a design environment where system board devices may potentially use many different supply voltages, which can ultimately lead to voltage conflicts. However, STSMIA832 device has been designed to work with a 3.6 V input tolerance.
PAGE 10
Application information 3.3 STSMIA832 Power saving at the inputs All internal blocks of the input circuitry are shutdown by turning off the bias currents for the subLVDS receivers. This eliminates the power associated with any dynamic activity on the input pins. With no pull-up and pull-down resistors, any remaining current drawn by an input is known as leakage current (IL), which ranges from 1 µA to 4 µA typical.
PAGE 11
STSMIA832 Application information Figure 9. STSMIA832 load capacitance and rise and fall time of LVTTL parallel outputs 3.7 Board layout To obtain the maximum benefit from the noise and EMI reductions of subLVDS, attention should be paid to the layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference from other signals and take full advantage of the noise canceling of the differential signals.
PAGE 12
Application information STSMIA832 Figure 10. Bypass decoupling capacitors Table 3.
PAGE 13
STSMIA832 Maximum ratings 4 Maximum ratings Table 5. Absolute maximum ratings Symbol VDD Parameter Value Unit -0.5 to 4.6 V -0.5 to (VDD + 0.5) V Main supply voltage VL Secondary supply voltage VD SubLVDS data bus input voltage (D+, D-) -0.5 to 4.6 V VSTRB SubLVDS clock bus input voltage (STRB+, STRB-) -0.5 to 4.6 V VI DC input voltage (SYNC_SEL, CLASS_SEL, EN) -0.5 to 4.6 V VO DC output voltage (D1-D8, H-SYNC, V-SYNC, CLK) -0.5 to (VL + 0.
PAGE 14
Electrical characteristics 5 STSMIA832 Electrical characteristics Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25 °C, and VDD = 2.8 V, VL = 1.8 V. Table 7. Symbol Electrical characteristics Parameter Test conditions VCM Common mode input voltage VTHL Receiver input low threshold (1) VTHH Receiver input high threshold II Input leakage current (D+, D-, STRB+, STRB-) IS Supply current (IL + IDD) ISOFF (1) Shutdown supply current (IL+ IDD) Min.
PAGE 15
STSMIA832 Electrical characteristics Over recommended operating conditions unless otherwise noted. Typical values are referred to TA = 25 °C and VDD = 2.8 V, VL = 1.8 V, RT = 100 Ω ± 1%, CL = 10 pF. Table 9. Symbol Switching characteristics Parameter Test conditions Min. Typ. Max. Unit tr Rise time LVTTL output voltage (10% to 90%) 1.9 2.5 ns tf Fall time LVTTL output voltage (90% to 10%) 1.6 2.5 ns 6.3 8.5 ns 6.9 8.5 ns 5.2 6.5 ns 5.2 6.5 ns 6.8 8.5 ns 6.4 8.5 ns 6.
PAGE 16
Electrical characteristics Table 9. Symbol STSMIA832 Switching characteristics (continued) Parameter Test conditions Min. Typ. Max. Unit tEN Enable delay time (EN to V-SYNC, H-SYNC) trEN = 2.0ns (10% to 90%) tfEN = 2.0ns (90% to 10%) 20 µs tDIS Disable delay time (EN to V-SYNC, H-SYNC) trEN = 2.0ns (10% to 90%) tfEN = 2.
PAGE 17
STSMIA832 6 Frame structure Frame structure Figure 11. Frame structure in VGA case (allowed synchronization codes sequence) Figure 12. Bit order in synchronization codes and data, LSB first (example start of frame), image frame structure Note: LSB (bytewise least significant bit first).
PAGE 18
Timing diagram 7 STSMIA832 Timing diagram Unless otherwise specified TA = 25°C. Figure 13. Disabled sync mode (SYNC_SEL = GND) (D1-D8 will transmit the input data DIN, including SYNC CODE) and CLASS_SEL = VL Note: 18/25 DATA_IN and STROBE are the input signals, CLKH is an internal signal i.e internal extracted clock having half frequency respect to the external clock. All others are output signals.
PAGE 19
STSMIA832 Timing diagram Figure 14. Enabled sync mode (SYNC_SEL = VDD) (D1-D8 will transmit the input data DIN, excluding SYNC CODE) and CLASS_SEL = VL Note: DATA_IN and STROBE are the input signals, CLKH is an internal signal i.e internal extracted clock having half frequency respect to the external clock. All others are output signals.
PAGE 20
Package mechanical data 8 STSMIA832 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
PAGE 21
STSMIA832 Package mechanical data TFBGA25 mechanical data mm. mils. Dim. A Min. Typ. Max. Min. Typ. Max. 1.0 1.1 1.16 39.4 43.3 45.7 A1 0.25 A2 0.78 b 0.25 D 2.9 D1 E 9.8 0.86 30.7 0.30 0.35 9.8 11.8 13.8 3.0 3.1 114.2 118.1 122.0 2 2.9 3.0 33.9 78.8 3.1 114.2 118.1 E1 2 78.8 e 0.5 19.7 SE 0.25 9.8 122.
PAGE 22
Package mechanical data STSMIA832 Tape & reel TFBGA25 mechanical data mm. inch. Dim. Min. Typ. A Min. Typ. 330 13.2 Max. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 22/25 Max. 0.504 0.519 14.4 0.567 Ao 3.3 0.130 Bo 3.3 0.130 Ko 1.60 0.063 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.
PAGE 23
STSMIA832 Order code 9 Order code Table 10.
PAGE 24
Revision history STSMIA832 10 Revision history Table 11. Document revision history Date Revision 13-Mar-2006 1 Initial release. 3-May-2006 2 Modified table 3 - output. 03-Jun-2009 3 Modified Figure 9 on page 11. 28-Sep-2009 4 Added row ESD Table 5 on page 13. 13-May-2010 5 Modified ISOFF Table 7 on page 14, added tOSLH1, HL2 Table 9 on page 15.
PAGE 25
STSMIA832 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.