Datasheet

Pin configuration STPMC1
8/77 Doc ID 15728 Rev 7
2 Pin configuration
Figure 2. Pin connections (top view)
MOP
SCS
V
DD
V
SS
V
CC
LED
SDATD
SCLNLC
XTAL1
XTAL2
SYN
V
SSA
MON
V
OTP
DAH
DAR
CLK
DAN
DAT
DAS
STPMC1
MOP
SCS
V
DD
V
SS
V
CC
LED
SDATD
SCLNLC
XTAL1
XTAL2
SYN
V
SSA
MON
V
OTP
DAH
DAR
CLK
DAN
DAT
DAS
STPMC1
Table 2. Pin description
Pin n° Symbol Type
(1)
Name and function
1 MON D / P O Programmable output pin, see
Ta bl e 5
2 MOP D / P O Programmable output pin, see Ta bl e 5
3 SCS D I Digital input pin, see Tabl e 5
4V
DD
A O 1.8 V output of internal low drop regulator which supplies the digital core
5V
SS
A GND Ground level for pad-ring and power supply return
6V
CC
P I Supply voltage
7V
OTP
P I Supply voltage for OTP cells
8 DAH D I Input for non-multiplexed ΔΣ signals
9 DAR D I Input for multiplexed ΔΣ R-phase signals
10 DAS D I Input for multiplexed ΔΣ S-phase signals
11 DAT D I Input for multiplexed ΔΣ T-phase signals
12 DAN D I Input for multiplexed ΔΣ PTAT and neutral signal
13 CLK D O 2 mA clock output for STPMSx devices
14 V
SSA
A GND Ground level of core
15 SYN D I/O Programmable input/output pin, see
Tabl e 5
16 XTAL2 A Crystal oscillator pin
17 XTAL1 A Crystal oscillator pin
18 SCLNLC D I/O Programmable input/output pin, see
Tabl e 5
19 SDATD D I/O Programmable input/output pin, see Tabl e 5
20 LED D O Programmable output pin, see Ta bl e 5
1. A: Analog, D: Digital, P: Power, I: Input, O: Output, GND: Ground