Datasheet

Theory of operation STPMC1
66/77 Doc ID 15728 Rev 7
1. collect all addresses of CFG bits to be permanently set into some list
2. clear all OTP shadow latches
3. set the system signal RD
4. connect a current source of at least +14 V, 1 mA to 3 mA to VOTP
5. wait for VOTP voltage is stable
6. set one OTP shadow latch from the list
7. set the system signal WE
8. wait for 300 µs
9. clear the system signal WE
10. clear the OTP shadow latch which was set in step 6
11. until all wanted CFG bits are permanently set, repeat steps 5 to 11
12. disconnect the current source
13. wait for VOTP voltage is less than 3V
14. clear the system signal RD
15. read all data records, in the last two of them there is read back of CFG bits
16. if verification of CFG bits fails and there is still chance to pass, repeat steps 1 to 16
For set or clear steps, apply the timing shown in timing for data records reading with proper
signal on the SDATD. For step 15, apply the timing shown in timing for writing configuration
and mode bits.
For permanent set of the TSTD bit, which causes no more writing to the configuration bits,
the procedure above must be conducted in such way that steps 6 to 13 are performed in
series during single period of active SCS because the idle state of SCS would make the
signal TSTD immediately effective which in turn, would abort the procedure and possibly
destroy the device due to clearing of system signal RD and so, connecting all gates of 3 V
NMOS sense amplifiers of already permanently set CFG bits to the VOTP source.