Datasheet

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This is information on a product in full production.

November 2012 Doc ID 15728 Rev 7 1/77

STPMC1

Programmable poly-phase energy calculator IC

Datasheet − production data

Features

■ Supports 1-, 2- or 3-phase WYE and Delta

services, from 2 to 4 wires

■ Computes cumulative active and reactive wide-

band and fundamental harmonic energies

■ Computes active and reactive energies, RMS

and momentary voltage and current values for

each phase

■ Supports Rogowski coil, current transformer,

Shunt or Hall current sensors

■ Exclusive ripple-free energy calculation

algorithm

■ Programmable pulsed output

■ Stepper motor outputs

■ Neutral current, temperature, and magnetic

field monitoring

■ OTP memory for configuration and calibration

■ SPI interface

■ Supports IEC 62052-11 / 62053-21 / 62053-23

standards

■ Less than 0.1 % error over 1:1000 dynamic

range

Applications

■ Power metering

Description

The STPMC1 device functions as an energy

calculator and is an ASSP designed for effective

energy measurement in power line systems

utilizing Rogowski, current transformer, Shunt or

Hall current sensors. Used in combination with

one or more STPMSx ICs, it implements all the

functions needed in a 1-, 2- or 3-phase energy

meter. It can be coupled with a microprocessor for

multi-function energy meters, or it can directly

drive a stepper motor for a simple active energy

meter. The calculator has five input data pins. The

first three receive the voltage and current

information of the phases. In fact, each data input

processes two ΔΣ signals, multiplexed in time and

generated by the STPMSx device. The fourth

input receives multiplexed ΔΣ signals also, and

can be used to sense the neutral current or

another signal - temperature, for example. The

fifth input data pin accepts non-multiplexed ΔΣ

signals and it can be used for sensing the

magnetic field information from a Hall sensor.

Four internal hard-wired DSP (digital signal

processing) units perform all the computations on

the ΔΣ streams in real time by means of ΔΣ

arithmetic blocks. This allows the achievement of

very high computation precision with fast and

efficient digital architecture. All the data recorded

by the STPMC1 are accessible through an SPI

port, which is also used to configure and calibrate

the device. The configuration and calibration data

can be saved in a 112-bit OTP block, or

dynamically set in microprocessor-based meters.

TSSOP20

Table 1. Device summary

Order code Temperature range Package Packaging

STPMC1BTR - 40 to 85 °C TSSOP20 (tape and reel) 2500 parts per reel

www.st.com

Summary of content (77 pages)

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STPMC1 Programmable poly-phase energy calculator IC Datasheet − production data Features ■ Supports 1-, 2- or 3-phase WYE and Delta services, from 2 to 4 wires ■ Computes cumulative active and reactive wideband and fundamental harmonic energies ■ Computes active and reactive energies, RMS and momentary voltage and current values for each phase ■ Supports Rogowski coil, current transformer, Shunt or Hall current sensors ■ Exclusive ripple-free energy calculation algorithm ■ Programmable pulsed ou
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Contents STPMC1 Contents 1 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Application . . . . . . . . . . . . . . .
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STPMC1 Contents 9.10.4 9.11 Energy to frequency conversion (configuration bits: APL, KMOT, LVS, FUND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.12 Using STPMC1 in microcontroller based meter - peripheral operating mode (configuration bits: APL, KMOT, LVS, FUND) . . . . . . . . . 33 9.13 Driving a stepper motor - standalone operating mode (configuration bits: APL, LVS, KMOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.
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Contents STPMC1 10.4 Energy integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.5 Fundamental power calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STPMC1 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures STPMC1 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. 6/77 STPMC1 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STPMC1 Functional block diagram 1 Functional block diagram Figure 1. STPMC1 device block diagram VDD VCC Linear Vregs VBG Band Gap VOTP POR 112 OTP CONFIGURATORS BIAS XTAL1 Clock Generator XTAL2 CLK 0 DAx 1 STEPPER DRIVER DAx-C Energy to Freq Converters xDSP DAx-V MOP MON LED VSSA 0 DAN 1 DAN-C SPI Interface NDSP DAN-V VSS DAH ENH SCL Note: SCS SYN SDA DAx stands for DAR, DAS, DAT, and xDSP stands for RDSP, SDSP, TDSP.
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Pin configuration STPMC1 2 Pin configuration Figure 2. Pin connections (top view) LED MOP SDATD SCS SCLNLC VDD VSS VCC VOTP Table 2. STPMC1 MON XTAL1 XTAL2 SYN VSSA DAH CLK DAR DAN DAS DAT Pin description Pin n° Symbol Type (1) 1 MON D/PO Programmable output pin, see Table 5 2 MOP D/PO Programmable output pin, see Table 5 3 SCS DI Digital input pin, see Table 5 4 VDD AO 1.
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STPMC1 Maximum ratings 3 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit - 0.3 to 6 V ± 150 mA VCC DC input voltage IPIN Current on any pin (sink/source) VID Input voltage at all pins -0.3 to VCC + 0.3 V VOTP Input voltage at OTP pin - 0.3 to 25 V ESD Human body model (all pins) ± 3.
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Functions STPMC1 4 Functions Table 5.
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STPMC1 Application 5 Application Figure 3. Application schematic in standalone operating mode N RST Stepper Counter 3 V to 5.5 V Current Sensor STPMS1 Voltage Sensor VCC VOTP MON MOP LED Current Sensor STPMS1 Voltage Sensor DAR SCS DAS SYN-NP Negative power SCL-NC No load condition SDA-TD Tamper Detection STPMC1 DAT DAN Current Sensor DAH CLK STPMS1 Pulsed output VDD XTAL1 XTAL2 VSS VSSA Voltage Sensor Current Sensor Figure 4.
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Application Table 6. STPMC1 Typical external components Function Component Value Tolerance Unit Reads or writes to a calculator device via SPI and performs computation Microprocessor --- --- --- Crystal oscillator 4.194 8.192 4.915 9.
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STPMC1 6 Electrical characteristics Electrical characteristics (VCC = 5 V, TA= - 40 to + 85 °C, 100 nF across VCC and VSS; 1 µF across VDD and VSSA, unless otherwise specified). Table 7. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit 5 400 Hz 3.17 5.5 V 7 mA Energy measurement accuracy fBW Effective bandwidth Limited by digital filtering General Section VCC Operating supply voltage ICC Supply current.
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Electrical characteristics Table 7. STPMC1 Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit Crystal oscillator VIH Input high voltage VIL Input low voltage Iin Input current on XTAL2 Rp External resistor Cp External capacitors fXTAL1 Nominal output frequency fMCLK Internal clock frequency fCLK 1.2 VCC =5.3V V 0.6 V -1 +1 µA 1 4 MΩ 22 pF 4.000 4.194 4.915 8.000 8.192 9.830 8.000 8.192 9.
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STPMC1 Terminology 7 Terminology 7.1 Measurement error The error associated with the energy measured by the STPMC1 is defined as: Percentage Error = SPMC1(reading) − True Energy True Energy 7.2 Conventions The lowest analog and digital power supply voltage is called VSS which represents the system ground (GND). All voltage specifications for digital input/output pins are referred to GND. Positive currents flow into a pin. “Sinking current” is the current flowing into the pin, and so it is positive.
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Terminology STPMC1 7.3 Notation Table 8.
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STPMC1 Typical performance characteristics 8 Typical performance characteristics Figure 5. Supply current vs. supply voltage, TA = 25°C (fXTAL1 = 4.194 MHz, fXTAL1 = 8.192 MHz) 8 7,5 ICC (mA) 7 6,5 6 5,5 ICC 25°C 5 ICC -40°C 4,5 ICC 85°C 4 3 3,5 4 4,5 5 5,5 6 VCC (V) Digital voltage regulator: line - load regulation. (fXTAL1 = 0; 100 nF across VCC and VSS; 1 µF across VDD and VSSA; TA = 25 °C) 2,5 2 1,5 VDD (V) Figure 6.
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Typical performance characteristics Figure 7.
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STPMC1 Theory of operation 9 Theory of operation 9.1 General operation The STPMC1 (also called a calculator) is an ASSP designed for effective measurement in power line systems utilizing the Rogowski coil, current transformer, Shunt or Hall current sensors. This device, used with the STMicroelectronics STPMSx companion chip (an analog front-end device), can be implemented as standalone or as a peripheral in a microprocessor based 1-, 2- or 3-phase energy meter.
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Theory of operation STPMC1 These four multiplexed signals are separated, by a digital de-multiplexer, back into eight ΔΣ signals, called streams. The signal coming from the voltage channel of the STPMSx is named with the suffix V, while the stream coming from the current channel is named with the suffix C. For example, the voltage stream of the S-phase is named DAS-V.
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STPMC1 Theory of operation The calculator, thanks to its flexibility, can work in all worldwide distribution network standards.
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Theory of operation STPMC1 source for the linear regulator. Also, this module produces several bias currents and voltages for all other analog modules and for the OTP module. 9.3 Resetting the STPMC1 (status bit HLT) The STPMC1 has no reset pin. The device is automatically reset by the power-on-reset detection circuit (POR) when the VCC crosses the 2.5 V value, but it can be reset also through the SPI interface through a dedicated remote reset request (RRR) command (see paragraph 9.21 for RRR details).
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STPMC1 Theory of operation reason, all blocks of the digital part, except the SPI interface, are held in a reset state for 125 ms after a power on reset (see Section 9.3). The second task of the clock generator is to provide all necessary clocks for the digital part. In this task, a MDIV and FR1 programming bits are used to inform the device about the nominal frequency value from XTAL1 (fXTAL1). Four nominal frequencies are possible through proper setting of the MDIV and FR1 bits (see Table 10).
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Theory of operation STPMC1 is 300 Hz signal. The ZCR signal is available on the MOP pin only when the STPMC1 works as a peripheral with the configuration bit APL=0. Figure 9. ZCR signal 9.6 Period and line voltage measurement (status bits: LIN, BFR, LOW, BFF) From voltage channels, a base frequency signal LIN is obtained, which is high when the line voltage is rising and it is low when the line voltage is falling, so that, LIN signal represents the sign of dv/dt.
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STPMC1 Theory of operation If the counted number of fMCLK/8 pulses between two trailing edges of LIN is lower than the 216 equivalent pulses, the base frequency exceeds the upper limit. In this case, such error must be repeated three times, in order to set the error flag BFR, as shown in Figure 10. Figure 10. LIN and BFR behavior when fline > fMCLK/216 The in-band base frequency resets the flag BFR.
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Theory of operation STPMC1 Each ACx register contains a 20-bit accumulator of the relative phase current IX [Ah] and an 8-bit register carrying the information about phase delay between voltage channels. The SWM mode is indicated by status bit NAH =0: ● Bit NAH=0 (SWM on) happens when BFR=1 and RMS value of current signal is IX > IXmax/4096 = 16 (IXmax = 216). In this case frequency is out of limits and RMS current IX is big enough, so it is accumulated in the corresponding ACx phase register.
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STPMC1 Theory of operation information about this signal is also available in the status bit BIL, one per each phase (see Table 32). The three phase status bit BIL is the AND of each phase status bit BIL. The no-load condition occurs when the product between UX and IX register values is below a given value. This value can be set by the LTCH configuration bits. Four different no-load threshold values can be chosen according to the two LTCH bits as reported in Table 14.
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Theory of operation STPMC1 error occurs the correspondent phase bit BCF is set. When the ΔΣ signal becomes correct again the BCF flag is cleared immediately. The 3-ph status bit BCF is the OR of each phase bit BFC, but it takes into account also the connection of the neutral wire (DAN-I stream). The other error condition occurs if the MOP, MON and LED pin outputs signals are different from the internal signals that drive them.
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STPMC1 Theory of operation ∑I X > Imax 256 Where: Imax = 216 Σ IX = IR + IS + IT + IN for SYS = 0, 1, 2, 3, 4, 7 Σ IX = IS + IT for SYS = 5, 6 Bit BCS is set according to Table 15 Table 15.
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Theory of operation STPMC1 Figure 11. Currents of the three phase system in example The value IMAX corresponds to the maximum current value hold by each RMS current register (internal value FFFF). It is a function of the sensor type, sensitivity and of the current channel gain.
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STPMC1 Theory of operation Example 6: 3-ph system - BCS = 1 Let us consider a three-phase, four wires system where: IR = 5 A IS = 5 A IT = 3.2 A IN = 0 A The tamper is evaluated because IR + IS +IT +IN = 13.2 A > 0,703125 A = IMAX / 256 In this case sIRMS = 0,449901 A > 0,4125 A = (IR + IS +IT +IN) / 32 Then BCS = 1.
PAGE 32
Theory of operation STPMC1 Whatever the SYS bits setting (indicating phases presence and configuration), bit BSF is always calculated, but it is valid only in cases SYS is 0, 1, 2 and 3. In fact in this case all the three phase voltage signals (uR, uS, uT) are available and can be checked, as shown in 0. In cases SYS is 4, 5, 6, 7, only two or one voltage signal are available (uS and/or uT), so that the sequence cannot be checked. Bit BSF is always set in the status byte, but it must be ignored.
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STPMC1 Theory of operation EMI tamper condition is not available as internal status signal, but it is available (in OR with other tamper conditions) on the SDATD pin of the device. In peripheral application mode it is possible to detect EMI tamper comparing the value of the 16-bit DCuN and of the 12-bit RMSuN to the threshold through a microcontroller. 9.
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Theory of operation STPMC1 Example 10: energy registers LSB value for SYS = 0, 1, 2, 4, 5, 6, 7 C = 64000 pulses/kWh = 17.7 Hz*kW KP = KF = 15.258 *10-6 Wh KQ = KR = 15.258 *10-6 VArh This means that the reading of 0x00001 in the active energy register represents 15.258 µWh, while 0xFFFFF represents 16 Wh. Example 11: Energy registers LSB value for SYS = 3 C = 64000 pulses/kWh = 17.7 Hz*kW KP = 15.258 *10-6 Wh KF = 30.517 *10-6 Wh KQ = KR = 30.
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STPMC1 Theory of operation Table 18. LED pin configuration for APL = 0 LVS (1 bit) FUND (1 bit) KMOT (2 bits) LED energy output 0 R 0 Active energy wide band P 2 S 3 T 0 3-ph 1 0 Active energy fundamental F C 2 S 3 T 0 3-ph 1 R 0 Reactive energy wide band Q C 2 S 3 T 0 3-ph 1 1 C (1) R 1 1 Freq 3-ph 1 0 Phase R 1 Reactive energy fundamental R C 2 S 3 T 1. C is the number of pulses per kWh set with calibration.
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Theory of operation STPMC1 From signal PΣ (3-ph active energy), stepper motor driving signals MA and MB (see Figure 12) are generated by means of internal divider, mono-flop and decoder and brought to MOP and MON pins. Figure 12. Stepper driving signals Hi MON Low Hi MOP Low The numbers of pulses per kWh on MOP and MON outputs (CM) is related to the number of pulses on LED pin (C, see par. 9.11) following the table below. Table 20.
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STPMC1 Theory of operation LED pin configuration for APL = 2, 3 Table 21. APL (2 bits) KMOT (2 bits) LED energy output Phase Freq 2 - Active energy wide band P 3-ph C 0 C/64 1 C/128 3 9.14 Active energy wide band P 3-ph 2 C/32 3 C/256 Negative power accumulation (configuration bit ABS, status bit SIGN) The ABS bits govern energy accumulation in case of negative power; they only affect active power P and fundamental active power F.
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Theory of operation STPMC1 Figure 13. Phase delay tRS tST tTR The ACR, ACS and ACT registers (bits [7:0], see paragraph 9.17.7) holds the information needed for this calculation. Let us indicate tRS, tST, tTR, the delays between R, S and T phases.
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STPMC1 Theory of operation Example 12: Phase delay calculation fXTAL1 = 4 MHz; MDIV = 0; FR1 = 0 → fMCLK = 8 MHz fLINE = 50 Hz → T = 20 ms; ACR[7:0] = 0101 1010 ACS[7:0] = 0010 0000 ACT[7:0] = 0000 0101 Asr[12] = 0 Asr[10:0] = 000 0101 00102 = 82 Art[12] = 0 Art[10:0] = 000010110102 = 90 ( ) Asr [12 ] time Asr = ⎛⎜ Asr [10 : 0] − 211 ⎝ 82μs ⇒ ⋅ 360° = +1,5° 20ms ( ) time Art = ⎛⎜ Art[10 : 0] − 211 ⎝ 90μs ⇒ ⋅ 360 ° = +1,6° 20ms Art [12 ] ( ) 0 8 8 + 1⎞⎟ ⋅ = ⎛⎜ 00001010010 2 − 211 + 1⎞⎟ ⋅ = +82μs ⎠
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Theory of operation STPMC1 9.16 Calibration (configuration bits: PM, TCS, CIX, CVX, CCA, CCB, CPX) 9.16.1 Voltage and current channels calibration The 8-bit calibration values CVX and CIX (where X stands for N, R, S or T) are used as static data for the channel ΔΣ calibrators, multiplying their streams to the following factor: KX = (4096 - 1024 + 4CXX)/4096 (± 12.
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STPMC1 Theory of operation Equation 4 ϕphc = K PHC 360° ⋅ fline fphc ϕphc is the phase compensation in degree, KPHC is the calculated coefficient, fline is the frequency of voltage signal, fphc is the clock for phase compensation. The clock for phase compensation fphc can be derived as reported in Table 23 and Table 24 Table 23. fphc frequency settings MDIV (1 bit) PM (1 bit) HSA (1 bit) fCLK X 0 0 fXTAL1 / 8 X 0 1 fXTAL1 / 4 0 1 X fXTAL1 / 2 1 1 X fXTAL1 / 4 Table 24.
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Theory of operation STPMC1 Example 14: Phase compensation for PM = 0, TCS = 0 Phase shift current for -ϕphc: CPC[1] = 0 i CPX[0] CPX[1] CPX[2] CPX[3] CPC[0] 1 2 4 8 16 u Kphc = - (16 CPC[0] + CPX[3:0]) Phase shift current for ϕphc: CPC[1] = 1 CPX[0] CPX[1] CPX[2] CPX[3] i 1 2 4 8 u 16 Kphc = (16 - CPX[3:0]) Table 26. Phase compensation for PM = 0, TCS = 0, fline = 50 Hz fphc φphc Δφphc 524 kHz +0.550°, -1.064° 0.034° 614 kHz +0.469°, -0.908° 0.029° 8.192 MHz 1.
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STPMC1 Theory of operation Example 15: Phase compensation for PM = 0, TCS = 1 Phase shift current for -ϕphc: CPC[1] = 0 CPX[0] CPX[1] CPX[2] CPX[3] CPC[0] CpC[0] CpC[1] 1 2 4 8 16 32 64 i u Kphc = - (32 CpC[1:0] + 16 CPC[0] + CPX[3:0]) Phase shift current for ϕphc: CPC[1] = 1 CPX[0] CPX[1] CPX[2] CPX[3] CPC[0] CpC[0] i 1 2 4 8 16 32 u 64 Kphc = 64 - (32 CpC[0] + 16 CPC[0] + CPX[3:0]) Table 27.
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Theory of operation STPMC1 Example 16: Phase compensation for PM = 1 Phase shift current for -ϕphc: CPC[1] = 0 CPX[0] CPX[1] CPX[2] CPX[3] CPC[0] CpC[0] CpC[1] 1 2 4 8 16 32 64 i u Kphc = - (32 CpC[1:0] + 16 CPC[0] + CPX[3:0]) Phase shift current for ϕphc: CPC[1] = 1 CPX[0] CPX[1] CPX[2] CPX[3] CPC[0] CpC[0] i 1 2 4 8 16 32 u 64 Kphc = 64 - (32 CpC[0] + 16 CPC[0] + CPX[3:0]) Table 28. Phase compensation for PM = 1, fline = 50 Hz fphc φphc Δφphc 2.097 MHz +0.549°, -1.
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STPMC1 Theory of operation An asymmetrical compensation is implemented by multiplying the phase current with α and the neutral current with β and these values are subtracted from neutral and phase currents respectively, as shown below: Table 29.
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Theory of operation STPMC1 iCT = α iN + α iS + β iR iCN = α iT + β iS + γ iR 9.17 Data records map There are seven groups of four data records available, each consisting of a parity nibble (see paragraph 9.17.8) and 28-bit data field. The data records have fixed position of reading. This means that no addressing of records is necessary. It is up to an application to decide how many records should read out from the device. If an application sends to device a precharge command (see paragraph 9.
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STPMC1 Theory of operation 0.4 PRD: ● period: 12-bit line period measurement (see paragraph 9.6). By default it is calculated from R-phase signal, if it is missing from S-phase then from T-phase. The value of the period can be calculated from the decimal value of period as: Equation 10 T= ● 9.17.2 period ⋅ 2 6 fMCLK DC uN: 16-bit DC component of voltage channel of NDSP. It may be DAN-V or DAH according to the value of ENH bit.
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Theory of operation STPMC1 Equation 11 ⎛ sIRMS = ⎜ ⎝ ● iX ⎞ ∑ 4 ⎟⎠ RMS iN MOM: 16-bit momentary value of neutral current Note: In systems 3-phase, no neutral, uST, uTR, uRS replace uR, uS, uT respectively. 9.17.3 Group 2 data records Figure 16. Group 2 data records DER parity uR RMS iR RMS DES parity uS RMS iS RMS DET parity uT RMS iT RMS DEN parity uN RMS iN RMS 4 bit 12 bit 16 bit 2.
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STPMC1 9.17.4 Theory of operation Group 3 data records Figure 17. Group 3 data records 20 bit 8 bit DAR parity R-phase active energy wide band R-phase status DAS parity S-phase active energy wide band S-phase status DAT parity T-phase active energy wide band T-phase status CF0 parity 4 bit bits [27..0] of configurators 20 bit 3.1 DAR: ● R-phase active energy wide band: 20-bit accumulator of R phase active energy wide band ● R-phase status: 8-bit R phase status (see Table 32).
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Theory of operation 9.17.5 STPMC1 Group 4 data records Figure 18. Group 4 data records 20 bit 8 bit DRR parity R-phase reactive energy R-phase status DRS parity S-phase reactive energy S-phase status DRT parity T-phase reactive energy T-phase status CF1 parity bits [55..28] of configurators 4 bit 20 bit 4.1 DRR: ● R-phase reactive energy: 20-bit accumulator of R phase reactive energy. ● R-phase status: 8-bit R phase status (see Table 32).
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STPMC1 9.17.6 Theory of operation Group 5 data records Figure 19. Group 5 data records 20 bit 8 bit DFR parity R-phase active energy fundamental R-phase status DFS parity S-phase active energy fundamental S-phase status DFT parity T-phase active energy fundamental T-phase status CF2 parity bits [83..56] of configurators 4 bit 20 bit 5.
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Theory of operation 9.17.7 STPMC1 Group 6 data records Figure 20. Group 6 data records 20 bit 8 bit ACR parity iR RMS Ah accumulator if bad uR R-phase elapsed ACS parity iS RMS Ah accumulator if bad uS S-phase elapsed ACT parity iT RMS Ah accumulator if bad uT T-phase elapsed CF3 parity bits [111..84] of configurators 4 bit 20 bit 6.1 ACR: ● iR RMS SWM accumulator: 20-bit accumulator of R phase current in SWM mode (see paragraph 9.
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STPMC1 Theory of operation Example 17: Parity calculation Let us calculate parity of DMR, the first register of second group: DMR: 9.
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Theory of operation Table 32.
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STPMC1 Theory of operation Each configuration bit can be written sending a byte command to STPMC1 through its SPI interface. See paragraph 9.21 for details on SPI operation. A system signal WE (see paragraph 9.20) is used in order to do the permanent write of some OTP bit. There is also a special high voltage input pad VOTP, which delivers the power level necessary for permanent write to OTP cell. The STPMC1 can work either using the data stored in the OTP cells or the data from the shadow latches.
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Theory of operation Table 33. STPMC1 Configuration bits map (continued) Address Name N. of bits Description IMPORTANT: The decimal value indicated in this column represents the value of the configuration bits with MSB in bold.
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STPMC1 Table 33. Theory of operation Configuration bits map (continued) Address Name N. of bits Description IMPORTANT: The decimal value indicated in this column represents the value of the configuration bits with MSB in bold. 7-BIT Binary DEC 0010101 21 PM 1 Precision meter: - PM=0: Class 1, - PM=1: Class 0.1 0010110 22 FR1 1 Selection of measurement clock value: - FR1=0: fMCLK =8.192 MHz, - FR1=1: fMCLK =9.
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Theory of operation Table 33. STPMC1 Configuration bits map (continued) Address Name N. of bits Description IMPORTANT: The decimal value indicated in this column represents the value of the configuration bits with MSB in bold.
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STPMC1 Table 33. Theory of operation Configuration bits map (continued) Address Name N. of bits Description IMPORTANT: The decimal value indicated in this column represents the value of the configuration bits with MSB in bold. 7-BIT Binary DEC 1101110 110 ENH 1 Fifth data input enable: - ENH=0: Voltage#0=DAN, - ENH=1: Voltage#0=DAH 1101111 111 CHK 1 Reserved – Must be always set to 1 9.
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Theory of operation STPMC1 to boost the VCC supply voltage of the STPMC1 to generate the VOTP voltage (14 V to 20 V) needed to program the OTP antifuse elements. WE (write Enable): This mode signal is used to permanently write to the OTP antifuse element. When this bit is not set, any write to the configuration bit is recorded in the shadow latches. When this bit is set the writing is recorded both in the shadow latch and in the OTP antifuse element.
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STPMC1 Theory of operation the SCS status. If SCS is low, SCLNCL is the input of serial bit synchronization clock signal. When SCS is high, SCLNLC determines idle state of the SPI. SDATD: is the data pin. If SCS is low, the operation of SDATD is dependent on the status of SYN pin. If SYN is high SDATD is the output of serial bit data (read mode) if SYN is low SDATD is the input of serial bit data signal (write mode). If SCS is high SDATD is input of idle signal.
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Theory of operation 9.21.2 STPMC1 Reading data records Data record reading takes place most often when there is an on-board microcontroller in an application. This microcontroller is capable of reading all measurement results and all system signals (configuration, calibration, status, mode). Again, the time step can be as short as 30 ns. There are two phases of reading, called latching and shifting. Latching is used to sample results into transmission latches.
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STPMC1 Theory of operation The first read out byte of the data record is the least significant byte (LSB) of the data value and of course, the fourth byte is the most significant byte (MSB) of the data value. Each byte can be further divided into a pair of 4-bit nibbles, most and least significant nibble (msn, lsn). This division makes sense with the MSB of the data value because the msn holds the parity code. Figure 23.
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Theory of operation Table 35. STPMC1 Functional description of commands Bit pos. 76543210 D0000000 DAAAAAAA D1101111 Command (X, D, A = {0, 1}) CFG000=D, (shadow of first configurator, TSTD) (shadow of any configurator, a = AAAAAA2 < 11100002) CFGa=D, CFG111=D, (shadow of last configurator, CHK) Example 18: Setting a configuration bit To set the configuration bit 47 (part of the R-phase current channel calibrator) to 0, we must convert the decimal 47 to its 7-bit binary value: 0101111.
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STPMC1 Theory of operation t3: data value is placed in SDA t4: SDA value is stable and shifted into the device t3 −> t5 (> 10 µs): writing clock period t3 −> t5: 1 bit data value t5 −> t6: 6 bits address of the destination latch t6 −> t7: 1 bit EXE command t8: end of SPI writing t9: SPI enters idle state 9.21.
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Theory of operation STPMC1 1. collect all addresses of CFG bits to be permanently set into some list 2. clear all OTP shadow latches 3. set the system signal RD 4. connect a current source of at least +14 V, 1 mA to 3 mA to VOTP 5. wait for VOTP voltage is stable 6. set one OTP shadow latch from the list 7. set the system signal WE 8. wait for 300 µs 9. clear the system signal WE 10. clear the OTP shadow latch which was set in step 6 11.
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STPMC1 10 Energy calculation algorithm Energy calculation algorithm For the purpose of simplicity the energy computation shown below is relative to only one phase.
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Energy calculation algorithm STPMC1 In case of shunt sensor (TCS = 1), an additional stage of internal digital differentiated produces the value: Equation 22 vd = dvu/dt = A ω cos (ω t) kDIF The shunt preamplifier, AD converter and calibrator produce the value: Equation 23 vs = i RS (AI/VREF) kI = i kS = C sin (ω t + ϕ) The 2nd stage internal integrations produce the values: Equation 24 vdi = ∫ vddt = A sin (ω t) kDIF kINT = A sin (ω t) Equation 25 vsi = ∫ vsdt = - (C / ω) cos (ω t + ϕ) kINT The frequency
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STPMC1 Energy calculation algorithm In case of a non Rogowski sensor, the corresponding products are: Equation 32 P1 = vd vsi = - AC kDIFkINT cos (ω t) cos (ω t + ϕ) = - AC [cos ϕ + cos (2 ω t + ϕ)] / 2 Equation 33 P2 = vdi vs = AC kDIFkINT sin (ω t) sin (ω t + ϕ) = AC [cos ϕ - cos (2 ω t + ϕ)] / 2 Then a subtraction of P1 from P2 is performed: Equation 34 P = (P2 - P1) / 2 = (AB cos ϕ) kINT / 2 = (UkDIkL cos ϕ) kINT / 2 = URMS IRMS cos ϕ kP where: Equation 35 kP = kD kL kINT This gives the same result for
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Energy calculation algorithm STPMC1 compensated stream of 16-bit voltage from the 2nd stage of filter (Equation 18 or Equation 26) is multiplied by the 16-bit current stream from the 2nd stage (Equation 16 or Equation 25) yielding: Equation 40 Q1 = vuiic vi = ABkINT sin (ω t) cos (ω t + ϕ) = - ABkINT [sin ϕ - sin (2 ω t + ϕ)] / 2 Equation 41 Q2 = ω / kINT vui vii = ABkINT cos (ω t) sin (ω t + ϕ) = ABkINT [sin ϕ + sin (2 ω t + ϕ)] / 2 In case of non Rogowski sensor, the corresponding products are: Equation
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STPMC1 10.3 Energy calculation algorithm Voltage and current RMS values calculation The IRMS value is produced from 16-bit value of Equation 16: Equation 49 1 T IRMSkLkINT = T ∫v 2 ii dt = B 0 1 2 The UiRMS is produced from stream and 16-bit value of Equation 15: Equation 50 1 T UiRMSkD = T ∫v 2 ui 1 2 dt = AkINT/ω 0 In case of non Rogowski sensor, the same dedicated RMS blocks produce some other values, because input values for the blocks are changed.
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Energy calculation algorithm STPMC1 The DSP performs also an integration of powers (P, Q) into energies: Equation 54 AW = URMS IRMS cos ϕ kP kUD Equation 55 AW = URMS IRMS sin ϕ kP kUD These integrators are implemented as up/down counters and they can roll over. 20-bit output buses of the counters are assigned as the most significant part of the energy data records. It is a responsibility of the application to read the counters at least every second so as not to miss any rollover.
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STPMC1 11 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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Package mechanical data STPMC1 TSSOP20 mechanical data mm. inch. Dim. Min. Typ. Max. A Min. Typ. Max. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.0256 BSC 0.60 8° 0° 0.75 0.018 8° 0.024 0.
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STPMC1 Package mechanical data Tape & reel TSSOP20 mechanical data mm. inch. Dim. Min. A Typ. Max. Min. 330 Max. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 Typ. 0.504 22.4 0.519 0.882 Ao 6.8 7 0.268 0.276 Bo 6.9 7.1 0.272 0.280 Ko 1.7 1.9 0.067 0.075 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.
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Revision history STPMC1 12 Revision history Table 36. Document revision history Date Revision 22-May-2009 1 Initial release. 03-Jul-2009 2 Updated: paragraphs 9.4, 9.16 and 9.17.8. 28-Jul-2009 3 Updated: paragraph 9.16.2. 19-May-2010 4 Added: Example 5: 3-ph system - BCS = 0 on page 29, Example 6: 3-ph system - BCS = 1 on page 31, Example 7: 1-ph system - BCS = 0 on page 31, Example 8: 1-ph system - BCS = 1 on page 31 and Equation 11: on page 48. Modified: paragraph 9.17.2 on page 47.
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STPMC1 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.