Datasheet

Theory of operation STPM10
34/53 Doc ID 17728 Rev 4
7.19 SPI interface
The SPI interface supports a simple serial protocol, which is implemented to enable
communication between some master system (microcontroller or PC) and the device.
Three tasks can be performed with this interface:
– remote resetting of the device
– reading data records
– writing the mode bits and the configuration bits
Four pins of the device are dedicated to this purpose: SCS, SYN, SCL and SDA.
SCS, SYN and SCL are all input pins, while SDA can be input or output according to
whether the SPI is in write or read mode. A high-level signal for these pins means a voltage
level higher than 0.75 x VCC, while a low-level signal means a voltage value lower than 0.25
x VCC.
The internal registers are not directly accessible. Instead, 32 bits of transmission latches are
used to pre-load the data before being read or written to the internal registers.
The condition in which SCS, SYN and SCL inputs are set to high level determines the idle
state of the SPI interface, and no data transfer occurs.
– SCS: enables SPI operation when low.
– SYN: operates different functions according to the status of the SCS pin. When
SCS is low, the SYN pin status selects if the SPI is in read (SYN = 1) or write
mode (SYN = 0). When the SCS is high and SYN is also high, the results of the
input or output data are transferred to the transmission latches.
– SCL: basically the clock pin of the SPI interface. This pin function is also controlled
by the SCS status. If SCS is low, SCL is the input of the serial bit synchronization
clock signal. When SCS is high, SCL is also high, determining the idle state of the
SPI.
– SDA: the data pin. If SCS is low, the operation of SDA is dependent on the status
of the SYN pin. If SYN is high, SDA is the output of the serial bit data (read mode).
If SYN is low, SDA is the input of the serial bit data signal (write mode). If SCS is
high, SDA is the input of the idle signal.
Any pin above has an internal weak pull-up mechanism of nominal 15 µA. This means that
when a pin is not forced by external signals, the state of the pin is logic high. A high state of
any input pin described above is considered an idle (not active) state. For the SPI to operate
correctly, the STPM10 must be correctly supplied as described in Section 7.6: Power supply.
An idle state of the SPI module is recognized when the signals of pins SYN, SCS, SCL and
SDA are in a logic high state. Any SPI operation should start from this idle state.
When SCS is active (low), signal SDATD should change its state at trailing edge of signal
SCLNLC and the signal SDATD should be stable at next leading edge of signal SCLNLC.
The first valid bit of SDATD is always started with activation of signal SCLNLC.