Datasheet

Theory of operation STPM10
18/53 Doc ID 17728 Rev 4
7.3 ΣΔ A/D converters
Analog-to-digital conversion in the STPM10 is carried out using two first-order Σ Δ
converters. The device performs A/D conversions of analog signals on two independent
channels in parallel. The current channel is multiplexed as a primary or secondary current
channel in order to perform the tamper function, if enabled. The converted Σ Δ signals are
supplied to the internal hard-wired DSP unit, which filters and integrates these signals in
order to boost the resolution and to yield all the necessary signals for the computations.
A Σ Δ modulator converts the input signal into a continuous serial stream of 1’s and 0’s at a
rate determined by the sampling clock. In the STPM10, the sampling clock is equal to
f
CLK
/4.
The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is
subtracted from the input signal. If the loop gain is high enough, the average value of the
DAC output (and therefore the bit stream) can approach that of the input signal level. When
a large number of samples are averaged, a very precise value for the analog signal is
obtained. This averaging is carried out in the DSP section, which implements decimation,
integration and DC offset cancellation of the supplied Σ Δ signals. The gain of the
decimation filters is 1.004 for the voltage channel and 0.502 for the current channel. The
resulting signal has a resolution of 11 bits per voltage channel and 16 bits per current
channel.
Figure 14. First-order ΣΔ A/D converter
DAC
-
+
Integrator
f
CLK
/4
Input analog signal
Output digital signal
Σ
∫