Datasheet

STPM01 Theory of operation
Doc ID 10853 Rev 8 37/60
As it is indicated above, the STPM01 includes 56 CFG bits. Normally, some of these bits
should be permanently set during production of application of STPM01 in order to protect
the application from power fails. Of course, if an application would include an on-board
microcontroller, it could reload the configuration and calibration values after power on restart
and so, the permanent set of STPM01 would not be necessary. But this is not very safe way
to do it, because due to some EMI even imposed to tamper the meter, the microcontroller
may become lost and during such state, it can change some system signals in the STPM01
or somebody can change the calibration and configuration by changing the software of on-
board microcontroller.
8.20 Mode signals
The STPM01 includes 8 mode signals located in the DFP data record, 3 of these are used
only for internal testing purposes while 5 are useful to change some of the operation of the
STPM01. The mode signals are not retained when the STPM01 supply is not available and
then they are cleared when a POR occurs but they are not cleared when a remote reset
command (RRR) is sent through SPI.
The mode signals bit can be written using the normal writing procedure of the SPI interface
(see SPI section).
Of course, we can clear the RD by clearing all system signals. The first way is to generate
POR signal but this way we clear and reset the whole device. An alternative way is to set the
TSTD bit in the shadow latches. This setting becomes effective after SCS goes to idle state
when the TSTD clears all system signals including itself but, it does not reset the whole
device.
110000 48
CRC 2
2-bit unsigned data for calibration of RC oscillator.
CRC=0, or CRC=3 cal=0%
CRC=1, cal=+10%;
CRC=2, cal=-10%.
110001 49
(1)
110010 50
NOM 2
2-bit modifier of nominal voltage for Single Wire Meter.
NOM=0: K
NOM
=0.3594 / NOM=1: K
NOM
=0.3906 / NOM=2: K
NOM
=0.4219 /
NOM=3: K
NOM
=0.4531;
110011 51
(1)
110100 52 ADDG 1
Selection of additional gain on current channels:
ADDG=0: Gain+=0 / ADDG=1: Gain+=8
110101 53 CRIT 1
Selection of tamper threshold:
CRIT =0: 12,5% / CRIT =1: 6,25%
110110 54 LVS 1
Type of stepper selection:
LVS=0: pulse width 31.25 ms, 5V, / LVS=1: pulse width, 156.25 ms, 3V
110111 55 1 Reserved
1. IMPORTANT: This bit represents the MSB of the decimal value indicated in the description column.
Table 16. Configuration bits map (continued)
Address
Name
n. of
bits
Description
(1)
6-bit
binary
DEC