Datasheet

Theory of operation STPM01
32/60 Doc ID 10853 Rev 8
When STPM01 is used in peripheral mode all these signal can be read through the SPI
interface. See paragraph 16 for details on the Status bit location in the STPM01 data
records.
In standalone mode the BIL signal is available in SCLNLC pin and the BIT signal in the
SDATD pin. All the other signals can be read only through SPI interface.
8.18 Programming the STPM01
Data records
The STPM01 has 8 internal data records registers. Every data record consists of 4-bit parity
code and 28-bit data value where the parity code is computed from the data value, which
makes total of 32 bits or 4 bytes.
The figure below shows the data records structure with the name of the contained
information.
Each bit of parity nibble is defined as odd parity of all seven corresponding bits of data
nibbles.
Table 15. Status bit description
Bit # Name Description Condition
0 BIL No load condition
BIL=0: No load condition not detected
BIL=1: No load detected
1BCF∑ Δ signals status
BCF=0: ∑ Δ signals alive
BCF=1: one or both ∑ Δ signals are stacked
2 BFR Line frequency range
BFR=0: Line frequency inside the 45Hz-65Hz range
BFR=1: Line frequency out of range
3 BIT Tamper condition
BIT=0: Tamper not detected;
BIT=1: Tamper detected;
4 MUX Current channel selection
MUX=0: Primary current channels selected by the tamper module;
MUX=1: Secondary current channels selected by the tamper
module;
5 LIN Trend of the line voltage
LIN=0: line voltage is going from the minimum to the maximum value.
(Δv/Δt >0);
LIN=1: line voltage is going from the maximum to the minimum value.
(Δv/Δt < 0);
6 PIN Output pins check
PIN=0: the output pins are consistent with the data
PIN=1: the output pins are different with the data, this means some
output pin is forced to 1 or 0.
7 HLT Data Validity
HLT=0: the data records reading are valid.
HLT=1: the data records are not valid. A reset occurred and a restart
is in progress.