Datasheet

Theory of operation STPM01
20/60 Doc ID 10853 Rev 8
8.5 Period and line voltage measurement
The period module measures the period of the base frequency of the voltage channel and
checks if the voltage signal frequency is within the f
CLK
/2
17
to f
CLK
/2
15
band. To do this, the
LIN signal is produced, which is low when the line voltage is rising, and high when the line
voltage is falling. This means that the LIN signal is the sign of dv/dt. With further elaboration,
the ZCR signal is also produced. On the trailing edge of LIN (line frequency) the period
counter starts counting up pulses of the f
CLK
/4 reference signal. The LIN signal is available
on the status bit register (see Ta bl e 1 5 ).
If the counted number of pulses between two trailing edges of LIN is higher than 2
15
, or if
the counting is never stopped (no LIN trailing edge) this means that the base frequency is
lower than f
CLK
/2
17
Hz and a BFR (base frequency range) error flag is set.
If the number of pulses counted between two trailing edges of LIN is lower than 2
13
, the
base frequency exceeds the limit (means it is higher than f
CLK
/2
15
. In this case, the error
must be repeated three consecutive times in order to set the BFR error flag.
For example, with a 4.194304 MHz oscillator frequency and MDIV bit clear (or 8.192 MHz
with MDIV set), f
CLK
/4 is 1048.576 MHz. If the line frequency is 30 Hz, the counted f
CLK
/4
pulses between two LIN trailing edges are 34952, more than 2
15
(32768 pulses). The BFR
low frequency limit is then:
f
CLK
/2
17
= 4194304/131072 = 32 Hz.
With the same clock frequency, if the line frequency is 130Hz, the f
CLK
/4 pulses between two
LIN trailing edges are 8066, more than 2
13
(8192). The BFR high frequency limit is then:
f
CLK
/2
15
= 4194304/32768 = 128 Hz.
When the line frequency re-enters the nominal band, the BFR flag is automatically reset.
This BFR error flag is also assembled as part of the 8-bit status register (see Ta bl e 1 5).
Figure 15. ZCR signal