Datasheet

Theory of operation STPM01
18/60 Doc ID 10853 Rev 8
The maximum differential input voltage is dependent on the selected gain according to the
following table.
The gain register is included in the device configuration register with the address names
PST and ADDG. The table below shows the gain configuration according to the register
values:
Note: If the device is used in configuration PST = 7 (primary channel with CT, secondary channel
with Shunt), the shunt Ks must always be equal to one fourth of the current transformer Ks.
Both the voltage and current channels implement an active offset correction architecture
which gives the benefit to avoid any offset compensation.
The analog voltage and current signals are processed by the ∑ Δ Analog to digital
converters that feed the hardwired DSP. The DSP implements an automatic digital offset
cancellation that make possible avoiding any manual offset calibration on the analog inputs.
Table 8. Gain of voltage and current channels
Voltage channels Current channels
Gain Max Input voltage (V) Gain Max input voltage (V)
4 ±0.30
8X ±0.15
16X ±0.075
24X ±0.05
32X ±0.035
Table 9. Configuration of current sensors
Primary Secondary Configuration Bits
Gain Sensor Gain Sensor PST (3 bits) ADDG (1 bit)
8
Rogowsky Coil
Disabled (No Tamper)
00
16 01
24 10
32 11
8CT 2 X
32 Shunt 3 X
8
Rogowsky Coil
8
Rogowsky Coil
40
16 16 4 1
24 24 5 0
32 32 5 1
8
CT
8CT6 X
8 32 Shunt 7 X