Datasheet

Features description STP24DP05
18/27 Doc ID 14714 Rev 5
7.5 Phase three: “resuming normal mode”
In order to re-enter normal mode, either the LE\DM pin or the sequence shown in the
following table can be used:
Note: For proper device operation the “entering detection” sequence must be followed by a
“resume mode” sequence, it is not possible to insert a consecutive equal sequence.
7.6 Shift register data flow control
The 8x3 shift registers have a default RGB sequence serial data flow as show in the block
diagram of Figure 2.
The data can be redirected by the DF0 and DF1 pins, these pins change the order of the
data flow according to the following table:
The status of pins DF0 and DF1 also influences the sequence of the error detection result
shifted out of the SDO pin.
Note: If the DF0 and DF1 pins are left floating, they are pulled-up to Vdd by internal pull-up
resistors. In such conditions, the shift register sequence is set to BGR.
Table 13. SPI sequence to resume in normal mode - truth table
CLK1°2°3°4°5°
OE-R\DM
HLHHH
LE\DM LLLLL
Table 14. Shifter register data flow control
Sequence DF0 DF1
BGR 1 1
BRG 0 1
RGB 1 0
GRB 0 0