Datasheet

STP24DP05 Features description
Doc ID 14714 Rev 5 17/27
After these five CLK cycles the device goes into “error detection mode” and at the 6
th
rise
front of CLK, the SDI data are ready for the sampling.
7.4 Phase two: “error detection”
The eight data bits must be set “1” in order to set all the outputs ON during detection. The
data are latched by LE\DM and after that the outputs are ready for the detection process.
When the microcontroller switches the OE-R\DM
to LOW, the device drives the LEDs in
order to analyze if an OPEN or SHORT condition has occurred.
The LED status is detected after at least 1 microsecond and after this time the
microcontroller sets OE-R\DM
in HIGH state and the output data detection result goes to the
microprocessor via the SDO pin.
Detection mode and normal mode both use the same format data. As soon as all the
detection data bits are available on the serial line, the device may go back to normal
operation mode. The result of the error detection is shifted out of the SDO pin providing 24
clock pulses. A faulty output is indicated as “0”, whereas a good output is indicated as “1”.
The result is shifted out according to the selected data flow (DF0 and DF1 status, see
Section 7.6).
Figure 14. SPI sequence to enter detection mode - time diagram
OE-R\DM
LE\DM
Figure 15. Detection diagram