Datasheet

Features description STP24DP05
16/27 Doc ID 14714 Rev 5
Figure 12. Detection circuit
7.3 Phase one: “entering detection mode”
From the “normal mode” condition the device can switch to the “error detection mode”
through a DM PIN set to LOW or a logic sequence on the OE-R\DM
and LE\DM pins as
shown in Figure 13, 14 and Tabl e 1 2:
Figure 13. EDM timing diagram using a DM pin
16
STP24DP05
24
23
Table 12. SPI sequence to enter detection mode - truth table
CLK1°2°3°4°5°
OE-R\DM
HLHHH
LE\DM LLLHL
OE-R\DM