Datasheet

Timing diagrams STP24DP05
12/27 Doc ID 14714 Rev 5
6 Timing diagrams
Figure 8. Timing diagram
Note: 1 Latch and output enable are level sensitive and are not synchronized with rising-or-falling
edge of CLK signal.
2 When LE\DM terminal is low level, the latch circuit holds the previous set of data.
3 When LE\DM terminal is high level, the latch circuit refreshes the new set of data
from the SDI chain.
4 When either OE-R\DM
, OE-G, or OE-B terminals are at low level, output terminals R\G\B1
to R\G\B8 respond to the data, either ON or OFF.
5 When either OE-R\DM
, OE-G, or OE-B terminals are at high level, all the data on the output
terminal R\G\B1 to R\G\B8 is switched off.
6 This device can customize the RGB sequence serial data flow by means of setting DF0 and
DF1 (refer to Table 1 4. ).