Datasheet
Table Of Contents
- Figure 1. Internal schematic diagram
- Table 1. Device summary
- 1 Electrical ratings
- 2 Electrical characteristics
- Table 5. On /off states
- Table 6. Dynamic
- Table 7. Switching times
- Table 8. Source drain diode
- 2.1 Electrical characteristics (curves)
- Figure 2. Safe operating area for D2PAK and TO-220
- Figure 3. Thermal impedance for D2PAK, TO-220 and TO-247
- Figure 4. Safe operating area for TO-247
- Figure 5. Output characteristics
- Figure 6. Transfer characteristics
- Figure 7. Gate charge vs gate-source voltage
- Figure 8. Static drain-source on-resistance
- Figure 9. Capacitance variations
- Figure 10. Normalized gate threshold voltage vs. temperature
- Figure 11. Normalized on-resistance vs temperature
- Figure 12. Source-drain diode forward characteristics
- Figure 13. Normalized V(BR)DSS vs temperature
- Figure 14. Output capacitance stored energy
- 3 Test circuits
- 4 Package mechanical data
- 5 Packaging mechanical data
- 6 Revision history

Electrical characteristics STB18N60M2, STP18N60M2, STW18N60M2
4/21 DocID024735 Rev 2
2 Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 5. On /off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
breakdown voltage
I
D
= 1 mA, V
GS
= 0 600 V
I
DSS
Zero gate voltage
drain current (V
GS
= 0)
V
DS
= 600 V 1 μA
V
DS
= 600 V, T
C
=125 °C 100 μA
I
GSS
Gate-body leakage
current (V
DS
= 0)
V
GS
= ± 25 V ±10 μA
V
GS(th)
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 μA234V
R
DS(on)
Static drain-source
on-resistance
V
GS
= 10 V, I
D
= 6.5 A 0.255 0.28 Ω
Table 6. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
C
iss
Input capacitance
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0
- 791 - pF
C
oss
Output capacitance - 40 - pF
C
rss
Reverse transfer
capacitance
-5.6-pF
C
oss eq.
(1)
1. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
Equivalent output
capacitance
V
DS
= 0 to 480 V, V
GS
= 0 - 164.5 - pF
R
G
Intrinsic gate
resistance
f = 1 MHz, I
D
= 0 - 5.6 - Ω
Q
g
Total gate charge
V
DD
= 480 V, I
D
= 13 A,
V
GS
= 10 V
(see Figure 16)
-21.5-nC
Q
gs
Gate-source charge - 3.2 - nC
Q
gd
Gate-drain charge - 11.3 - nC
Table 7. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d
(on) Turn-on delay time
V
DD
= 300 V, I
D
= 6.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 15 and Figure 20)
-12-ns
t
r
Rise time - 9 - ns
t
d
(off) Turn-off delay time - 47 - ns
t
f
Fall time - 10.6 - ns