Datasheet

Error detection mode functionality STP16DPPS05
22/34 Doc ID 15817 Rev 2
Figure 23. Error detection sequence
Ignore
On the rising edge of first CLK pulse after the detection, the SDO
provides the Output status f eedback with the sequence Out 15;
Out 14…Out 0.
In this case all the outputs are in f ault condition (Open or Short)
This OE/DM2 pulse put the
device in Normal Mode
Condition af ter EDM test
Turn ON the output with the OE/DM2 pin and wait 1 µs to
have the correct output status acquisition. During this time
a minimum of three CLK pulses are required (2 at the
beginning and 1 at the end) to rewrite the shif t register.
OE/DM2 and LE/DM1
sequence signals to
start the error
detection sequence
Feeding 16 bit of CLK signal af ter
entering the EDM, the SDI signal, set to
1, is loaded in the shift register
This LE/DM1 pulse latch
the data to the outputs