Datasheet

Detection mode functionality STP16DP05
16/31 Doc ID 13093 Rev 6
7 Detection mode functionality
7.1 Phase one: “entering in detection mode“
From the “normal mode” condition the device can switch to the “error mode” by a logic
sequence on the OE\DM2
and LE/DM1 pins as showed in the following table and diagram:
After these five CLK cycles the device goes into the “error detection mode” and at the 6
th
rise front of CLK the SDI data are ready for the sampling.
Table 12. Entering in detection truth table
CLK1°2°3°4°5°
OE/DM2
HLHHH
LE/DM1 LLLHL
Figure 15. Entering in detection timing diagram