Datasheet

Timing diagrams STP16DP05
10/31 Doc ID 13093 Rev 6
5 Timing diagrams
Note: OUTn = ON when Dn = H OUTn = OFF when Dn = L
Figure 7. Timing diagram
Note: 1 Latch and output enable are level sensitive and ARE NOT synchronized with rising-or-falling
edge of CALK signal.
2 When LE terminal is low level, the latch circuits hold previous set of data
3 When LE terminal is at high level, the latch circuits refresh new set of data from SDI chain.
4 When OE terminal is at low level, the output terminals - Out0 to Out15 respond to data in the
latch circuits, either '1' for ON or '0' for OFF
5 When OE terminal is at high level, all output terminals will be switched OFF.
Table 9. Truth table
CLOCK LE\DM1 OE\DM2 SERIAL-IN OUT0 ............. OUT7 ................ OUT15 SDO
H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15
L L Dn + 1 No change Dn - 14
H L Dn + 2 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13
X L Dn + 3 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13
X H Dn + 3 OFF Dn - 13