Datasheet

Timing diagrams STP16CPS05

10/27 Doc ID 12569 Rev 6

5 Timing diagrams

Note: OUTn = ON when Dn = H OUTn = OFF when Dn = L

Figure 7. Timing diagram

Note: 1 Latch and output enable terminals are Level-sensitive and are not synchronized with rising

or falling edge of CLK signal

2 When LE terminal is at low level, the latch circuit holds previous set of data

3 When LE terminal is at high level, the latch circuit refreshes new set of data from SDI chain

4 When OE

is at low level the output terminals Out 0 to Out 15 respond to data in the latch

circuits, either '1' for ON or '0' for OFF.

5 When OE

is at high level, all output terminals are switched OFF.

Table 9. Truth table

CLOCK LE OE

SERIAL-

OUT0

............. OUT7 ................ OUT15 SDO

H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15

L L Dn + 1 No change Dn - 14

H L Dn + 2 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13

X L Dn + 3 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13

X H Dn + 3 OFF Dn - 13