Datasheet

STP04CM05 Timing diagrams
Doc ID 14191 Rev 5 11/23
6 Timing diagrams
Figure 7. Timing diagram
Note: 1 Latch and output enable are level sensitive and are not synchronized with rising-or-falling
edge of CLK signal.
2 When LE terminal is low level, the latch circuit hold previous set of data.
3 When LE terminal is high level, the latch circuit refresh new set of data from SDI chain.
4 When OE terminal is at low level, the output terminal - Out 0 to Out 03 respond to data in the
latch circuits, either ‘1’ for ON or ‘0’ for OFF.
5 When OE terminal is at high level, all output terminals will be switched OFF.
OFF
OFF
OFF
OFF
ON
ON
ON
ON