Datasheet

STOTG04E Block description
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Table 21. Interrupt registers (*)
(*) Bit order is the same for all four interrupt related registers. Meaning of each register is described in Table 17.
6.9 I
2
C Bus interface
All of the STOTG04 transceiver registers are accessible through the I
2
C bus (see Figure 12). The device
contains a slave controller which provides communication with an external master. The I
2
C interface
consists of three pins:
• SDA (Serial Data);
• SCL (Serial Clock);
• ADR_PSW (is the LSB of the device address).
6.10 Device address
The USB-OTG transceiver has following 7-bit I
2
C device address:
The adr bit represents current state of the ADR_PSW device pin. It means that the address can be either
2Ch or 2Dh according to the ADR_PSW pin.
6.11 Bus protocol
Any device that sends data to the bus is defined as the transmitter. Any device that reads the data is the
receiver. The device that controls data transfers is the bus master, while the transmitter or receiver is the
slave device. The master initiates data transfers and provides the serial clock. The STOTG04 is always
the slave device.
Operation of the I
2
C bus is described by following figure 12.
Name Bit R Description
vbus_vld 0 0
A-device V
BUS
valid comparator
sess_vld 1 0 Session valid comparator
dp_hi 2 0 D+ pin is asserted high during SRP
id_gnd 3 0 ID pin grounded
dm_hi 4 0 D- pin is asserted high
id_float 5 0 ID pin floating
bdis_acon 6 0
Set when bdis_acon_en bit is set and transceiver asserts dp_pull-up after
detecting B-device disconnect
cr_int 7 0 Car-kit interrupt
010110adr