Datasheet

Block description STOTG04E
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Table 18. Control register 1
(1) State of the bit after reset.
Setting the bdis_acon_en bit enables automatic switching of the D+ pull-up resistor when the device
receives an SE0 longer than half of the bit period. This function should not be used in low-speed
operation.
Table 19. Control register 2
It is not possible to set vbus_drv, vbus_dischrg and vbus_chrg at the same time; the bit having higher
priority will remain set while the others will be cleared. Vbus_drv has higher priority than vbus_dischrg
which has higher priority than vbus_chrg.
Table 20. Control register 3
Name Bit
R
(1)
Description
Speed 0 1
0 = low-speed mode
1 = full-speed mode
Suspend 1 1
0 = normal operation
1 = power-down mode
dat_se0 2 0
0 = VP_VM mode
1 = DAT_SE0 mode
transp_en 3 0
Enable transparent I
2
C mode
bdis_acon_en 4 0 Enable A-device to connect if B-device disconnect detected
oe_int_en 5 0
When set and suspend = 1, then OE_TP_INT/ becomes
interrupt output
uart_en 6 0 Enable UART mode (higher priority than transp_en bit)
7 Reserved
Name Bit R Description
dp_pull-up 0 0 Connect D+ pull-up
dm_pull-up 1 0 Connect D- pull-up
dp_pull-down 2 1 Connect D+ pull-down
dm_pull-down 3 1 Connect D- pull-down
id_gnd_drv 4 0 Connect ID pin to ground
vbus_drv 5 0
Provide power to V
BUS
vbus_dischrg 6 0
Discharge V
BUS
through a resistor to ground
vbus_chrg 7 0
Charge V
BUS
through a resistor
Name Bit R Description
00Reserved
rec_bias_en 1 0 Enables transmitter bias even during USB receive
bidi_en 2 1
When set, then DAT_VP and SE0_VM pins become bidirectional
otherwise they are inputs only
bdir[0] 3 0
Direction of the drivers between DAT_VP↔DP and
SE0_VM↔DM in the UART mode
bdir[1] 4 1
audio_en 5 0 Enables car-kit interrupt detector
psw_en 6 0
Enables external charge pump control on the ADR_PSW pin.
Disables internal charge pump.
2V7_en 7 0 Enables 2.7V voltage regulation instead of 3.3V