Datasheet

STMPE811 Analog-to-digital converter
Doc ID 14489 Rev 6 31/65
ADC_CAPT ADC channel data capture
Address: 0x22
Type: R/W
Reset: 0xFF
Description:
To initiate ADC data acquisition.
ADC_DATA_CHn ADC channel data registers
Address: Add address
Type: R/W
Reset: 0x0000
Description:
ADC data register 0-7 (DATA_CHn=0 -7)
The ADC in STMPE811 operates on an internal RC clock with a typical frequency of
6.5 MHz. The total conversion time in ADC mode depends on the "SampleTime" setting,
and the clock division field 'Freq'.
The following table shows the conversion time based on 6.5 MHz, 3.25 MHz and 1.625 MHz
clock.
[1:0] ADC_FREQ: Selects the clock speed of ADC
00: 1.625 MHz typ.
01: 3.25 MHz typ.
10: 6.5 MHz typ.
11: 6.5 MHz typ.
76543 2 1 0
CH[7:0]
[7:0] CH[7:0]: ADC channel data capture
Write '1' to initiate data acquisition for the corresponding channel. Writing '0' has no effect.
Reads '1' if conversion is completed. Reads '0' if conversion is in progress.
11109876543 2 1 0
DATA[11:0]
[11:0] DATA[11:0]: ADC channel data
If TSC is enabled, CH3-0 is used for TSC and all readings to these channels give 0x0000
Table 14. ADC conversion time
Sample time
setting
Conversion time
in ADC clock
6.5 MHz
(154 ns)
3.25 MHz
(308 ns)
1.625 MHz
(615 ns)
000 36 5.5 µs (180 kHz) 11 µs (90 kHz) 22 µs (45 kHz)
001 44 6.8 µs (147 kHz) 13.6 µs (74 kHz) 27 µs (36 kHz)
010 56 8.6 µs (116 kHz) 17.2 µs (58 kHz) 34.4 µs (29 kHz)
011 64 9.9 µs (101 kHz) 19.8 µs (51 kHz) 39.6 µs (25 kHz)