SPI interface STMPE811
18/65 Doc ID 14489 Rev 6
Figure 7. SPI timing specification
t
CSCL
CS_n high to
first clock edge
300
−−
ns
t
CSZ
CS_n high to
tri-state on
MISO
1
−−
µs
Table 10. SPI timing specification (continued)
Symbol Description
Timing
Unit
Min Typ Max
