Datasheet

STMPE811 SPI interface
Doc ID 14489 Rev 6 17/65
5.2 SPI timing modes
The SPI timing modes are defined by CPHA and CPOL,CPHA and CPOL are read from the
"SDAT" and "A0" pins during power-up reset. The following four modes are defined
according to this setting.
The clocking diagrams of these modes are shown in ON reset. The device always operates
in mode 0. Once the bits are set in the SPICON register, the mode change takes effect on
the next transaction defined by the CS_n pin being deasserted and asserted.
5.2.1 SPI timing definition
Table 9. SPI timing modes
CPOL_N (SDAT pin) CPOL CPHA (ADDR pin) Mode
1000
1011
0102
0113
Table 10. SPI timing specification
Symbol Description
Timing
Unit
Min Typ Max
t
CSS
CS_n falling to
first capture
clock
1
−−
µs
t
CL
Clock low
period
500
−−
ns
t
CH
Clock high
period
500
−−
ns
t
LDI
Launch clock
to MOSI data
valid
−−
20 ns
t
LDO
Launch clock
to MISO data
valid
−−
330 µs
t
DI
Data on MOSI
valid
1
−−
µs
t
CCS
Last clock
edge to CS_n
high
1
−−
µs
t
CSH
CS_n high
period
2
−−
µs