Datasheet

I2C interface STMPE811
10/65 Doc ID 14489 Rev 6
4 I
2
C interface
The addressing scheme of STMPE811 is designed to allow up to 2 devices to be connected
to the same I
2
C bus.
Figure 4. STMPE811 I
2
C interface
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and be followed by the slave device address. Accompanying the slave device
address, is a read/write bit (R/W). The bit is set to 1 for read and 0 for write operation. If a
match occurs on the slave device address, the corresponding device gives an acknowledge
on the SDA during the 9
th
bit time. If there is no match, it deselects itself from the bus by not
responding to the transaction.
Figure 5. I
2
C timing diagram
Table 6. I
2
C address
ADDR0 Address
00x82
10x88
ADDR0
SC
LK
SDAT
SC
LK
SDAT
GND
VCC
STMPE811
AI00589
SDA
P
tSU:STOtSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STAtBUF
SP